Patents by Inventor Yi Su

Yi Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240144467
    Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.
    Type: Application
    Filed: January 8, 2024
    Publication date: May 2, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Huei Chen, Pei-Chao Su, Xiaomeng Chen, Chan-Ming Chang, Shih-Yung Chen, Hung-Yi Chung, Kuang-Shing Chen, Li-Jou Lee, Yung-Cheng Lin, Wei-Chen Wu, Shih-Chang Wang, Chien-An Lin
  • Publication number: 20240145554
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure, the method includes forming a buffer layer over a substrate. An active layer is formed on the buffer layer. A top electrode is formed on the active layer. An etch process is performed on the buffer layer and the substrate to define a plurality of pillar structures. The plurality of pillar structures include a first pillar structure laterally offset from a second pillar structure. At least portions of the first and second pillar structures are spaced laterally between sidewalls of the top electrode.
    Type: Application
    Filed: January 11, 2024
    Publication date: May 2, 2024
    Inventors: Yao-Chung Chang, Chun Lin Tsai, Ru-Yi Su, Wei Wang, Wei-Chen Yang
  • Patent number: 11973209
    Abstract: A positive electrode active material for a secondary battery includes a lithium composite transition metal oxide including nickel (Ni), cobalt (Co), and manganese (Mn), wherein the lithium composite transition metal oxide has a layered crystal structure of space group R3m, includes the nickel (Ni) in an amount of 60 mol % or less based on a total amount of transition metals, includes the cobalt (Co) in an amount greater than an amount of the manganese (Mn), and is composed of single particles.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: April 30, 2024
    Assignee: LG Chem, Ltd.
    Inventors: Eun Hee Lee, Seong Bae Kim, Young Su Park, Yi Rang Lim, Hong Kyu Park, Song Yi Yang, Byung Hyun Hwang, Woo Hyun Kim
  • Publication number: 20240132523
    Abstract: This application relates to solid forms and salt forms of the PD-1/PD-L1 inhibitor 4,4?-(((((2,2?-dichloro-[1,1?-biphenyl]-3,3?-diyl)bis(azanediyl))bis(carbonyl))bis(1-methyl-1,4,6,7-tetrahydro-5H-imidazo[4,5-c]pyridine-2,5-diyl))bis(ethane-2,1-diyl))bis(bicyclo[2.2.1]heptane-1-carboxylic acid), including processes of preparation thereof, where the solid forms and salt forms are useful in the treatment of various diseases including infectious diseases and cancer.
    Type: Application
    Filed: November 21, 2023
    Publication date: April 25, 2024
    Inventors: Zhongjiang Jia, Shili Chen, Yi Li, Timothy Martin, Bo Shen, Naijing Su, Jiacheng Zhou, Qun Li
  • Publication number: 20240127734
    Abstract: Embodiments of this application provide a display panel and a terminal device, and are applied to the field of terminal technologies. The display panel is provided with a connection line, a signal line in an edge display area is extended to a center display area through the connection line and connected to a fan-out lead, and a sequence of input first display data is changed by using a drive chip, so that when an arrangement number of each fan-out lead is different from an arrangement number of a signal line connected to the fan-out lead, second display data output by the drive chip can be transmitted to a correct signal line. In addition, a same drive chip can be applied to different terminal devices, to improve utilization of the drive chip and reduce design costs of the drive chip.
    Type: Application
    Filed: May 16, 2022
    Publication date: April 18, 2024
    Inventors: Yi Su, Yabin An, Haiming He
  • Patent number: 11960141
    Abstract: Provided is a lens assembly driving module including a photographing lens assembly, a first driving mechanism and a second driving mechanism. The photographing lens assembly includes N lens elements and has an optical axis passing through the N lens elements. The first driving mechanism drives at least N/2 said lens elements to move along the optical axis of the photographing lens assembly. The second driving mechanism enables a relative distance along the optical axis of two adjacent ones of the N lens elements to vary. Therefore, any specific one of the lens elements is capable of being driven to optimize optical imaging resolution of various fields of view independently within a real shot at different object distances.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: April 16, 2024
    Assignee: LARGAN DIGITAL CO., LTD.
    Inventors: Heng-Yi Su, Hao-Jan Chen, Ming-Ta Chou, Te-Sheng Tseng
  • Patent number: 11963386
    Abstract: A display apparatus includes a base substrate, a light emitting structure disposed on the base substrate, and a thin film encapsulation layer disposed on the light emitting structure and including at least one inorganic layer and at least one organic layer. The at least one inorganic layer includes a high density layer having a density of greater than or equal to about 2.0 g/cm3 and a low density layer having a density of less than about 2.0 g/cm3. The high density layer and the low density layer are in contact with each other.
    Type: Grant
    Filed: September 2, 2022
    Date of Patent: April 16, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Chang Yeong Song, Won Jong Kim, Yi Su Kim, Jong Woo Kim, Hye In Yang, Woo Suk Jung, Yong Chan Ju, Jae Heung Ha
  • Patent number: 11962100
    Abstract: A dual-band antenna module includes a first antenna structure and a second antenna structure. The first antenna structure includes a first insulating substrate, a conductive metal layer, a plurality of grounding supports, and a first feeding pin. The second antenna structure includes a second insulating substrate, a top metal layer, a bottom metal layer, and a second feeding pin. The conductive metal layer is disposed on the first insulating substrate. The grounding supports are configured for supporting the first insulating substrate. The second insulating substrate is disposed above the first insulating substrate. The top metal layer and the bottom metal layer are respectively disposed on a top side and a bottom side of the second insulating substrate. The first frequency band signal transmitted or received by the first antenna structure is smaller than the second frequency band signal transmitted or received by the second antenna structure.
    Type: Grant
    Filed: August 7, 2022
    Date of Patent: April 16, 2024
    Assignee: Taiwan Inpaq electronic Co., Ltd.
    Inventors: Ta-Fu Cheng, Shou-Jen Li, Cheng-Yi Wang, Chih-Ming Su
  • Patent number: 11961453
    Abstract: A pixel drive circuit and a drive method thereof, a display panel, and a terminal device, which are applied to the field of terminal technologies. The pixel drive circuit includes a first reset module, a light-emitting control module, and a drive module, and both the first reset module and the light-emitting control module are connected to a light-emitting control signal terminal, where one of the first reset module and the light-emitting control module is turned on when the light-emitting control signal is at a high level, and the other of the first reset module and the light-emitting control module is turned on when the light-emitting control signal is at a low level. Therefore, by increasing the frequency of the light-emitting control signal to greater than 120 Hz, a problem of a phenomenon of frequent flickering on an image during low-brightness display may be improved.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: April 16, 2024
    Assignee: HONOR DEVICE CO., LTD.
    Inventors: Yi Su, Yabin An
  • Publication number: 20240109987
    Abstract: The present disclosure relates to a polyethylene resin composition capable of improving transparency and moisture barrier properties without deterioration in physical properties of a film, and a film including the same, wherein the polyethylene resin composition comprises a nucleating agent and a lubricant both containing a cation of a same metal selected from Group 2 or Group 12 metals.
    Type: Application
    Filed: August 31, 2022
    Publication date: April 4, 2024
    Applicants: LG Chem, Ltd., LG Chem, Ltd.
    Inventors: Hyun Mook Jeong, Dodam Kim, Yi Young Choi, Hee Su Oh
  • Publication number: 20240094841
    Abstract: Embodiments of this application provide a method applied to a signal synchronization system, a system, a stylus, and an electronic device. The system includes a stylus and an electronic device. The electronic device supports a first refresh rate and a second refresh rate. The method includes: after an electronic device is wirelessly connected to a stylus, the electronic device samples a downlink signal from the stylus based on a third refresh rate, where the third refresh rate is equal to a first refresh rate or a second refresh rate; and the stylus sends the downlink signal to the electronic device based on the third refresh rate, and samples an uplink signal from the electronic device at a fourth refresh rate, where the fourth refresh rate is the least common multiple of the first refresh rate and the second refresh rate.
    Type: Application
    Filed: January 14, 2022
    Publication date: March 21, 2024
    Inventors: Hang Li, Yi Su
  • Publication number: 20240090796
    Abstract: A foot sensor and analysis device, which includes a pressure sensing layer arranged inside the insole and a sensing module installed inside the insole. The sensing module is electrically coupled with the pressure sensing layer for receiving and processing detected electronic signals, where sensing module includes an inductance coil to perform wireless charging to the battery. The pressure sensing layer and the sensing module are integrally formed inside the insole.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 21, 2024
    Inventors: Yao-Sheng Chou, Hsiao-Yi Lin, Wei-Sheng Su, Hsing-Yu Chi
  • Publication number: 20240094497
    Abstract: An imaging lens module includes a casing, an imaging lens disposed to the casing, a lens carrier supporting the image lens, an elastic element connected to the lens carrier to provide the lens carrier with a translational degree of freedom along an optical axis, a frame connected to the elastic element such that the lens carrier is movable along the optical axis with respect to the frame, a variable through hole module coupled to the imaging lens and having a light passable hole with a variable aperture size, and a wiring assembly including a fixed wiring part at least partially located closer to the opening than the elastic element and a movable wiring part electrically connected to the fixed wiring part and the variable through hole module. The optical axis passes through lens elements of the imaging lens and the center of the variable through hole module.
    Type: Application
    Filed: January 10, 2023
    Publication date: March 21, 2024
    Applicant: LARGAN PRECISION CO., LTD.
    Inventors: Hao-Jan CHEN, Heng Yi SU, Ming-Ta CHOU, Te-Sheng TSENG
  • Publication number: 20240096835
    Abstract: A method of manufacturing an electronic package is provided, in which an electronic element is disposed on a carrier structure; a heat dissipation body of a heat dissipation structure is disposed on the electronic element via a heat dissipation material; the heat dissipation material is cured; supporting legs of the heat dissipation structure are fixed on the carrier structure via a bonding layer; and the bonding layer is cured. Therefore, the heat dissipation structure can be effectively fixed to the heat dissipation material and the bonding layer by completing the arrangements of the heat dissipation material and the bonding layer in stages.
    Type: Application
    Filed: November 16, 2022
    Publication date: March 21, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Pin-Jing SU, Liang-Yi HUNG, Yu-Po WANG
  • Patent number: 11936186
    Abstract: Provided are a method and apparatus for evaluating a degree of frequency regulation urgency of a generator set, a power system and a storage medium.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: March 19, 2024
    Assignees: STATE GRID FUJIAN ELECTRIC POWER COMPANY LIMITED, STATE GRID FUJIAN ELECTRIC POWER RESEARCH INSTITUTE, CHINA ELECTRIC POWER RESEARCH INSTITUTE COMPANY LIMITED
    Inventors: Zhenhua Xu, Risheng Fang, Ting Huang, Dahai Yu, Kewen Li, Xiangyu Tao, Daoshan Huang, Yi Su, Zhi Chen, Danyue Wu, Huiyu Zhang
  • Publication number: 20240087962
    Abstract: A semiconductor structure and method for manufacturing thereof are provided. The semiconductor structure includes a silicon substrate having a first surface, a III-V layer on the first surface of the silicon substrate and over a first active region, and an isolation region in a portion of the III-V layer extended beyond the first active region. The first active region is in proximal to the first surface. The method includes the following operations. A silicon substrate having a first device region and a second device region is provided, a first active region is defined in the first device region, a III-V layer is formed on the silicon substrate, an isolation region is defined across a material interface in the III-V layer by an implantation operation, and an interconnect penetrating through the isolation region is formed.
    Type: Application
    Filed: November 24, 2023
    Publication date: March 14, 2024
    Inventors: MAN-HO KWAN, FU-WEI YAO, RU-YI SU, CHUN LIN TSAI, ALEXANDER KALNITSKY
  • Publication number: 20240077657
    Abstract: An imaging lens assembly includes a first optical element and a low-reflection layer. The first optical element has a central opening, and includes a first surface, a second surface and a first outer diameter surface. The first outer diameter surface is connected to the first surface and the second surface. The low-reflection layer is located on at least one of the first surface and the second surface, and includes a carbon black layer, a nano-microstructure and a coating layer. The nano-microstructure is directly contacted with and connected to the carbon black layer, and the nano-microstructure is farther from the first optical element than the carbon black layer from the first optical element. The coating layer is directly contacted with and connected to the nano-microstructure, and the coating layer is farther from the first optical element than the nano-microstructure from the first optical element.
    Type: Application
    Filed: November 13, 2023
    Publication date: March 7, 2024
    Inventors: Wen-Yu TSAI, Heng-Yi SU, Ming-Ta CHOU, Chien-Pang CHANG, Kuo-Chiang CHU
  • Publication number: 20240077656
    Abstract: An imaging lens assembly includes a first optical element and a low-reflection layer. The first optical element has a central opening, and includes a first surface, a second surface and a first outer diameter surface. The first outer diameter surface is connected to the first surface and the second surface. The low-reflection layer is located on at least one of the first surface and the second surface, and includes a carbon black layer, a nano-microstructure and a coating layer. The nano-microstructure is directly contacted with and connected to the carbon black layer, and the nano-microstructure is farther from the first optical element than the carbon black layer from the first optical element. The coating layer is directly contacted with and connected to the nano-microstructure, and the coating layer is farther from the first optical element than the nano-microstructure from the first optical element.
    Type: Application
    Filed: November 13, 2023
    Publication date: March 7, 2024
    Inventors: Wen-Yu TSAI, Heng-Yi SU, Ming-Ta CHOU, Chien-Pang CHANG, Kuo-Chiang CHU
  • Patent number: 11908905
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure, the method includes forming a buffer layer over a substrate. An active layer is formed on the buffer layer. A top electrode is formed on the active layer. An etch process is performed on the buffer layer and the substrate to define a plurality of pillar structures. The plurality of pillar structures include a first pillar structure laterally offset from a second pillar structure. At least portions of the first and second pillar structures are spaced laterally between sidewalls of the top electrode.
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: February 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Chung Chang, Chun Lin Tsai, Ru-Yi Su, Wei Wang, Wei-Chen Yang
  • Patent number: D1022349
    Type: Grant
    Filed: November 1, 2023
    Date of Patent: April 9, 2024
    Inventor: Yi Su