Abstract: Devices and methods are provided for word line pulse width control for a static random access memory (SRAM) devices. An inverter within a pre-decoder circuit receives a first input of a clocked address. The inverter determines an output based on the clocked address. An electrical load of a decoder driver circuit of the SRAM device is modified based on the output. Current to a transistor coupled at a common node is provided. The transistor is configured to electrically couple a plurality of transistors of the decoder driver circuit within the SRAM device.

Abstract: A memory array includes a first column of memory cells, a second column of memory cells, a first pre-charge circuit, a second pre-charge circuit and a set of input output circuits. The first column of memory cells includes a first bit line, a first word line and a first bit line bar. The second column of memory cells includes the first bit line bar, a second word line and a second bit line. The first pre-charge circuit is coupled to the first bit line. The second pre-charge circuit is coupled to the first bit line bar. The first column of memory cells and the second column of memory cells are configured to share the first bit line bar. The first bit line and the first bit line bar are in a first plane. At least a portion of the first word line and at least a portion of the second word line are in a second plane intersecting the first plane.

Abstract: A memory array includes a first column of memory cells, a second column of memory cells, a first pre-charge circuit, a second pre-charge circuit and a set of input output circuits. The first column of memory cells includes a first bit line, a first word line and a first bit line bar. The second column of memory cells includes the first bit line bar, a second word line and a second bit line. The first pre-charge circuit is coupled to the first bit line. The second pre-charge circuit is coupled to the first bit line bar. The first column of memory cells and the second column of memory cells are configured to share the first bit line bar. The first bit line and the first bit line bar are in a first plane. At least a portion of the first word line and at least a portion of the second word line are in a second plane intersecting the first plane.

Abstract: A desk has a base that rests on an underlying floor surface, a work surface that is supported by the base, and a seat that is rotatably connected to the base for rotation between a first position, located in a conventional position behind the desk so a person may sit at the desk, and a second position, located to one side of the desk so that a person may instead stand at the desk. The seat is adjustable radially relative to its axis of rotation, vertically up and down relative to the floor surface, and angularly toward its axis of rotation.

Abstract: A memory array includes a first column of memory cells, a second column of memory cells and a set of switching elements. The first column of memory cells includes a first bit line, a first word line and a second bit line. The second column of memory cells includes the second bit line, a second word line and a third bit line. The first and second column of memory cells are configured to share the second bit line. The first and second bit lines are in a first plane. At least a portion of the first word line and at least a portion of the second word line are in a second plane intersecting the first plane. An amount of bit line switching elements in the set of bit line switching elements is equal to N*2, where N is an amount of columns of memory cells in the memory array.

Abstract: A memory device includes a memory cell, a local bit line, a data line, first and second pass gate circuits, and a sense amplifier. The local bit line is coupled to the memory cell. The first pass gate circuit is coupled to the local bit line and the data line and is configured to couple the local bit line to the data line. The second pass gate circuit is coupled to the data line and the global bit line and is configured to couple the data line to the global bit line. The sense amplifier is coupled to the data line.

Abstract: A memory device includes a memory cell, a local bit line, a data line, first and second pass gate circuits, and a sense amplifier. The local bit line is coupled to the memory cell. The first pass gate circuit is coupled to the local bit line and the data line and is configured to couple the local bit line to the data line. The second pass gate circuit is coupled to the data line and the global bit line and is configured to couple the data line to the global bit line. The sense amplifier is coupled to the data line.

Abstract: A memory device comprises a tracking control circuit for controlling the write operation or the read operation of the memory device. The tracking control circuit comprises a plurality of tracking cells, wherein the timing characteristics of the tracking cells emulate the timing characteristics of a bit cell during a write operation or a read operation of the memory device. The memory device further comprises at least two reference word lines for configuring the number of tracking cells of the tracking control circuit; and a selection circuit configured to activate one or more of the at least two reference word lines.

Abstract: A semiconductor memory includes a first layer including at least a first memory cell, a second layer including at least a second memory cell, and a wordline shared by the first memory cell and the second memory cell. The first and second memory cells can be above or below the wordline and be coupled to different bit lines.

Abstract: A memory array includes a first column of memory cells, a second column of memory cells and a set of switching elements. The first column of memory cells includes a first bit line, a first word line and a second bit line. The second column of memory cells includes the second bit line, a second word line and a third bit line. The first and second column of memory cells are configured to share the second bit line. The first and second bit lines are in a first plane. At least a portion of the first word line and at least a portion of the second word line are in a second plane intersecting the first plane. An amount of bit line switching elements in the set of bit line switching elements is equal to N*2, where N is an amount of columns of memory cells in the memory array.

Abstract: A sit-up bench apparatus includes a base set, two supporting rod sets, two elastic sets and an extending rod set. The base set includes a seat body and a pivotal base. The aperture is formed at one end of the pivotal base. The supporting rod set is pivotally disposed at the pivotal base and includes a supporting rod and a first cylinder. The first cylinder is connected with the supporting rod. The elastic set is disposed at the pivotal base and connected between the two supporting rod sets and the base set. The elastic set includes a spring and an extending rod set. One end of the spring is coupled to the pivotal base. The extending rod set is disposed in the aperture and includes a supporting wheel disposed at one end of the extending rod set.

Abstract: A memory device comprises a tracking control circuit for controlling the write operation or the read operation of the memory device. The tracking control circuit comprises a plurality of tracking cells, wherein the timing characteristics of the tracking cells emulate the timing characteristics of a bit cell during a write operation or a read operation of the memory device. The memory device further comprises at least two reference word lines for configuring the number of tracking cells of the tracking control circuit; and a selection circuit configured to activate one or more of the at least two reference word lines.

Abstract: A parity bit generator module is disclosed that operates in a first direction or a second direction. In the first direction, the parity bit generator module generates parity bits for a first input datastream having information bits and combines these parity bits with the information bits of the input datastream to provide a first output datastream. Otherwise in a second direction, the parity bit generator module separates information bits from a second input datastream and generates parity bits from the information bits of the second input datastream to provide a second output datastream having the parity bits. In various exemplary embodiments, the bi-directional parity bit generator is implemented as part of an encoding/decoding module and/or an error-correcting code (ECC) data storage device.

Abstract: A sit-up bench apparatus includes a base set, two supporting rod sets, two elastic sets and an extending rod set. The base set includes a seat body and a pivotal base. The aperture is formed at one end of the pivotal base. The supporting rod set is pivotally disposed at the pivotal base and includes a supporting rod and a first cylinder. The first cylinder is connected with the supporting rod. The elastic set is disposed at the pivotal base and connected between the two supporting rod sets and the base set. The elastic set includes a spring and an extending rod set. One end of the spring is coupled to the pivotal base. The extending rod set is disposed in the aperture and includes a supporting wheel disposed at one end of the extending rod set.

Abstract: The modified rocking chair comprises a support stand, an adjusting assembly, and a carrying rack. The support stand has two curved bars, four support bars, a first connecting bar, and an elongated bar. The four support bars include two first support bars and two second support bars. The first connecting bar is mounted securely on the two curved bars. The elongated bar is mounted securely between the two second support bars. The adjusting assembly has a moving tube rotatably mounted on the elongated bar, and a limiting tube rotatably mounted on the first connecting bar and movably mounted around the moving tube. The carrying rack has a cushion. The moving tube moves towards the first connecting bar and through the limiting tube, and the support stand is folded to decrease the volume for improving the efficiency of transportation and storage.

Abstract: A memory array includes a first memory column having a first bit line, a first word line and a second bit line. The memory array also includes a second memory column having the second bit line, a second word line and a third bit line. The first memory column and the second memory column are configured to share the second bit line. The sharing of the second bit line facilitates sharing one or more memory array components between the first memory column and the second memory column.

Abstract: A memory device comprises a tracking control circuit for controlling the write operation or the read operation of the memory device. The tracking control circuit comprises a plurality of tracking cells, wherein the timing characteristics of the tracking cells emulate the timing characteristics of a bit cell during a write operation or a read operation of the memory device. The memory device further comprises at least two reference word lines for configuring the number of tracking cells of the tracking control circuit; and a selection circuit configured to activate one or more of the at least two reference word lines.

Abstract: A parity bit generator module is disclosed that operates in a first direction or a second direction. In the first direction, the parity bit generator module generates parity bits for a first input datastream having information bits and combines these parity bits with the information bits of the input datastream to provide a first output datastream. Otherwise in a second direction, the parity bit generator module separates information bits from a second input datastream and generates parity bits from the information bits of the second input datastream to provide a second output datastream having the parity bits. In various exemplary embodiments, the bi-directional parity bit generator is implemented as part of an encoding/decoding module and/or an error-correcting code (ECC) data storage device.

Abstract: A semiconductor memory includes a first layer including at least a first memory cell, a second layer including at least a second memory cell, and a wordline shared by the first memory cell and the second memory cell. The first and second memory cells can be above or below the wordline and be coupled to different bit lines.

Abstract: Exemplary embodiments for SRAM cells, new control units for SRAM systems, and embodiments of SRAM systems are described herein. An SRAM cell is configured to receive a first input voltage signal and a second input voltage signal with a different value from the first input voltage signal, and to maintain a first stored value signal and a second stored value signal. A control circuit is configured to receive a first input voltage signal and a second input voltage signal, and controlled by a sleep signal, a selection signal, and a data input signal, so that the output of the control circuit is data sensitive to the data input signal. An SRAM system comprises a plurality of SRAM cells, controlled the disclosed control circuit wherein an SRAM cell has two input voltage signals controlled by a data input signal and its complement signal respectively.