Patents by Inventor Yi-Wei Chen

Yi-Wei Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11222784
    Abstract: A semiconductor device includes a gate structure on a substrate, in which the gate structure includes a silicon layer on the substrate, a titanium nitride (TiN) layer on the silicon layer, a titanium (Ti) layer between the TiN layer and the silicon layer, a metal silicide between the Ti layer and the silicon layer, a titanium silicon nitride (TiSiN) layer on the TiN layer, and a conductive layer on the TiSiN layer.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: January 11, 2022
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Tzu-Hao Liu, Yi-Wei Chen, Tsun-Min Cheng, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Po-Chih Wu, Pin-Hong Chen, Chun-Chieh Chiu, Tzu-Chieh Chen, Chih-Chien Liu, Chih-Chieh Tsai, Ji-Min Lin
  • Publication number: 20210399353
    Abstract: A backup battery system includes a charging-discharging module and a battery module. The charging-discharging module includes a first connector and a first engaging member. The battery module is detachably connected to the charging-discharging module and includes a second connector corresponding to the first connector and a second engaging member corresponding to the first engaging member. When the battery module is connected to the charging-discharging module, the first connector is joined with the second connector and the first engaging member is fixed to the second engaging member.
    Type: Application
    Filed: July 21, 2020
    Publication date: December 23, 2021
    Applicants: LITE-ON ELECTRONICS (GUANGZHOU) LIMITED, Lite-On Technology Corporation
    Inventors: Shin Yi Low, Wen-Lung Liang, Yi-Wei Chen, Wei-Hao Liang
  • Patent number: 11177083
    Abstract: A key structure includes a keycap, a base plate and a wing-type supporting element. When the keycap is depressed in response to an external force, a first frame and a second frame of the wing-type supporting element are pushed by each other through protrusion structures and rotating shafts. Consequently, the first frame and the second frame can be swung relative to the base plate.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: November 16, 2021
    Assignee: PRIMAX ELECTRONICS LTD.
    Inventors: Ming-Han Wu, Che-Wei Yang, Yi-Wei Chen, Chien-Hung Liu, Lei-Lung Tsai
  • Patent number: 11145475
    Abstract: A keyboard device includes plural key structures. Each key structure includes a plate assembly, a keycap, a connecting member and a buffering element. The plate assembly has a hollow region. The keycap is located over the plate assembly. The connecting member is connected between the keycap and the plate assembly. The keycap is connected with the connecting member through at least one hook of the keycap. The keycap is movable upwardly or downwardly relative to the plate assembly through the connecting member. The buffering element is installed on the plate assembly. The buffering element is extended in a direction toward the keycap and penetrated through the hollow region of the plate assembly. While the keycap is moved downwardly and the at least one hook of the keycap is contacted with the buffering element, there is the gap between the keycap and the plate assembly.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: October 12, 2021
    Assignee: PRIMAX ELECTRONICS LTD.
    Inventors: Ming-Han Wu, Che-Wei Yang, Yi-Wei Chen, Chien-Hung Liu, Chen-Hsuan Hsu
  • Patent number: 11099656
    Abstract: A low-height key structure includes a keycap, a supporting plate, a connecting element, a circuit board and an elastic element. The circuit board is disposed on the supporting plate. A switch element is installed on the circuit board. The connecting element is connected with the keycap and the supporting plate. The keycap is movable upwardly or downwardly relative to the supporting plate through the connecting element. The elastic element is arranged between the keycap and the circuit board. The elastic element includes a contacting part and an elastic support part, which are connected with each other. The contacting part includes a bowl-shaped concave structure. A raised structure is protruded from a middle region of a bottom side of the bowl-shaped concave structure. A top surface of the raised structure is at a level lower than or equal to a top surface of the contacting part.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: August 24, 2021
    Assignee: PRIMAX ELECTRONICS LTD.
    Inventors: Bo-An Chen, Yi-Wei Chen
  • Patent number: 11088023
    Abstract: A method of forming a semiconductor structure includes providing a material layer having a recess formed therein. A first tungsten metal layer is formed at a first temperature and fills the recess. An anneal process at a second temperature is then performed, wherein the second temperature is higher than the first temperature.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: August 10, 2021
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Pin-Hong Chen, Chih-Chieh Tsai, Tzu-Chieh Chen, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Tsun-Min Cheng, Yi-Wei Chen, Wei-Hsin Liu
  • Patent number: 11067865
    Abstract: A display apparatus includes a first substrate, a second substrate, a display medium, a pixel structure, a read-out transistor, a first insulating layer, a light-sensing structure, and a color filter pattern. The display medium is disposed between the first substrate and the second substrate. The pixel structure is disposed between the display medium and the first substrate. The read-out transistor has a semiconductor pattern and a control terminal. The light-sensing structure is disposed between the second substrate and the display medium, and is electrically connected to the read-out transistor. The first insulating layer is disposed between the semiconductor pattern and the control terminal of the read-out transistor. The color filter pattern is disposed between the second substrate and the display medium. The first insulating layer has an opening located outside the light-sensing structure, and the color filter pattern fills the opening of the first insulating layer.
    Type: Grant
    Filed: January 14, 2021
    Date of Patent: July 20, 2021
    Assignee: Au Optronics Corporation
    Inventors: Chih-Chung Su, Shin-Shueh Chen, Yi-Wei Chen
  • Patent number: 11044026
    Abstract: A system and method of emulating radio device includes a multi-radio unit, a multi-radio unit controller and an under-test radio system. The multi-radio unit includes multiple radio circuits, in which the radio circuits are configured to generate multiple radio emulated signals. The multi-radio unit controller coupled to the multi-radio unit is configured to generate multiple control signals to the multi-radio unit, in which the control signals are configured to control the radio emulated signals sent by the multi-radio unit. The under-test radio system is configured to receive the radio emulated signals generated by the multi-radio unit, and configured to generate multiple data corresponding to the radio emulated signals.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: June 22, 2021
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: En-Cheng Liou, Ta-Sung Lee, Yi-Wei Chen, Kai-Ten Feng
  • Publication number: 20210174872
    Abstract: Multi-stage content addressable memory devices are described. Some embodiments relate to memory devices including a plurality of rows of memory cells, multiple match lines and multiple pre-charge circuits. A first row of the plurality of rows includes a first segment and a second segment. The first segment may include a first subset of the memory cells of the first row and the second segment may include a second subset of the memory cells of the first row. The first match line is coupled to the memory cells of the first subset, and the second match line is coupled to the memory cells of the second subset. The first pre-charge circuit is configured to pre-charge the first match line to a first pre-charge voltage, and the second pre-charge circuit is configured to pre-charge the second match line to a second pre-charge voltage different from (e.g., greater than) the first pre-charge voltage.
    Type: Application
    Filed: November 3, 2020
    Publication date: June 10, 2021
    Applicant: MEDIATEK Singapore Pte. Ltd.
    Inventors: Chetan Deshpande, Gajanan Sahebrao Jedhe, Ritesh Garg, Gaurang Prabhakar Narvekar, Yi-Wei Chen
  • Publication number: 20210151442
    Abstract: A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.
    Type: Application
    Filed: January 29, 2021
    Publication date: May 20, 2021
    Inventors: Yi-Wei Chen, Hsu-Yang Wang, Chun-Chieh Chiu, Shih-Fang Tzou
  • Patent number: 11010584
    Abstract: A display device includes a pixel array substrate, a sensing element substrate, and a display medium layer. The display medium layer is disposed between the pixel array substrate and the sensing element substrate. The sensing element substrate includes a substrate, a switch element, an insulation layer, an electrically conductive layer, a signal line, a sensing layer, and an electrode layer. The switch element is disposed on the substrate. The insulation layer covers the switch element. The electrically conductive layer is disposed on the insulation layer. The signal line is electrically connected to the electrically conductive layer. The sensing layer covers a top surface of the electrically conductive layer, a first side of the electrically conductive layer, and a second side of the electrically conductive layer. The electrode layer covers the sensing layer. The electrode layer is electrically connected to the switching element.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: May 18, 2021
    Assignee: Au Optronics Corporation
    Inventors: Shin-Shueh Chen, Che-Chia Chang, Shu-Wen Tzeng, Yi-Wei Chen, Pao-Yu Huang
  • Publication number: 20210143192
    Abstract: A display device, including a pixel array substrate and a sensor element substrate, is provided. The sensor element substrate overlaps the pixel array substrate, and includes a substrate, a switch element, and a photosensitive element. The switch element is located on the substrate. The photosensitive element is electrically connected to the switch element, and includes a transparent electrode, a sensing layer, a metal electrode, and a barrier layer. The sensing layer is located on the transparent electrode. The metal electrode is located on the sensing layer, and covers a first sidewall of the sensing layer. The barrier layer covers a first sidewall of the transparent electrode. The barrier layer is located between the metal electrode and the sensing layer, or between the transparent electrode and the sensing layer.
    Type: Application
    Filed: September 10, 2020
    Publication date: May 13, 2021
    Applicant: Au Optronics Corporation
    Inventors: Shin-Shueh Chen, Yi-Wei Chen
  • Publication number: 20210092108
    Abstract: A mechanism for building decentralized computer applications that execute on a distributed computing system. The present technology works within a web browser, client application, or other software and provides access to decentralized computer applications through the browser.
    Type: Application
    Filed: September 24, 2020
    Publication date: March 25, 2021
    Applicant: Magic Labs, Inc.
    Inventors: Fei-Yang Jen, Yi Wei Chen, Jaemin Jin, Hanyu Xue, Wentao Liu, Shang Li
  • Patent number: 10943909
    Abstract: A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: March 9, 2021
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yi-Wei Chen, Hsu-Yang Wang, Chun-Chieh Chiu, Shih-Fang Tzou
  • Publication number: 20210066005
    Abstract: A keyboard device includes plural key structures, a membrane circuit board and a flexible light shielding element. Each key structure includes a keycap. The keycap has a first end surface and a second end surface. The membrane circuit board is located under the keycap. The flexible light shielding element is arranged between the keycap and the membrane circuit board, and includes a bottom layer and plural stopping walls. Each stopping wall includes a wall body and a platform part. The wall body is protruded from the bottom layer and in the direction toward the keycap. An included angle is formed between the wall body and the bottom layer. The platform part is protruded from the wall body. The platform part is arranged between the second end surface of the keycap and the bottom layer. The platform part is contacted with the second end surface.
    Type: Application
    Filed: October 24, 2019
    Publication date: March 4, 2021
    Inventors: Ming-Han Wu, Yi-Wei Chen, Che-Wei Yang
  • Patent number: 10930517
    Abstract: A fin-shaped structure includes a substrate having a first fin-shaped structure located in a first area and a second fin-shaped structure located in a second area, wherein the second fin-shaped structure includes a ladder-shaped cross-sectional profile part. The present invention also provides two methods of forming this fin-shaped structure. In one case, a substrate having a first fin-shaped structure and a second fin-shaped structure is provided. A treatment process is performed to modify an external surface of the top of the second fin-shaped structure, thereby forming a modified part. A removing process is performed to remove the modified part through a high removing selectivity to the first fin-shaped structure and the second fin-shaped structure, and the modified part, thereby the second fin-shaped structure having a ladder-shaped cross-sectional profile part is formed.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: February 23, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Jiun Shen, Ssu-I Fu, Yen-Liang Wu, Chia-Jong Liu, Yu-Hsiang Hung, Chung-Fu Chang, Man-Ling Lu, Yi-Wei Chen
  • Publication number: 20210033935
    Abstract: The present disclosure provides a display device. The display device includes a substrate, a pixel array, a circuit bridge structure, a first trace region, a second trace region, and a display film layer. The pixel array is located on the substrate. The circuit bridge structure is located at one side of the pixel array. The first trace region is located between the pixel array and a first side of the circuit bridge structure. The second trace region is located at a second side opposite to the first side. The display film layer is located on the pixel array, and an orthogonal projection of the display film layer on the substrate is spaced apart from an orthogonal projection of the circuit bridge structure on the substrate.
    Type: Application
    Filed: May 20, 2020
    Publication date: February 4, 2021
    Inventors: Chih-Chung SU, Yi-Wei CHEN
  • Patent number: 10903328
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a shallow trench isolation (STI) in the substrate; removing part of the STI to form a trench in a substrate; forming an amorphous silicon layer in the trench and on the STI; performing an oxidation process to transform the amorphous silicon layer into a silicon dioxide layer; and forming a barrier layer and a conductive layer in the trench.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: January 26, 2021
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Po-Chun Chen, Chia-Lung Chang, Yi-Wei Chen, Wei-Hsin Liu, Han-Yung Tsai
  • Patent number: 10903245
    Abstract: A pixel array substrate including a substrate, a plurality of pixel structures and a scan device is provided. The pixel structures are arranged on the substrate along a first direction. Each pixel structure includes a data line, an active device and a pixel electrode. The active device has a semiconductor pattern, a source electrode and a drain electrode. The source electrode and the drain electrode are electrically connected to the data line and the pixel electrode respectively. The scan device includes a first and a second scan line. The first and the second scan line extend in the first direction and are electrically connected to each other. The active devices of the pixel structures are electrically connected to the first and the second scan line. The first and the second scan line respectively overlap two different regions of the semiconductor pattern of each active device.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: January 26, 2021
    Assignee: Au Optronics Corporation
    Inventors: Chih-Chung Su, Yi-Wei Chen
  • Publication number: 20200403077
    Abstract: A method for fabricating semiconductor device includes the steps of first forming a silicon layer on a substrate and then forming a metal silicon nitride layer on the silicon layer, in which the metal silicon nitride layer includes a bottom portion, a middle portion, and a top portion and a concentration of silicon in the top portion is greater than a concentration of silicon in the middle portion. Next, a conductive layer is formed on the metal silicon nitride layer and the conductive layer, the metal silicon nitride layer, and the silicon layer are patterned to form a gate structure.
    Type: Application
    Filed: September 4, 2020
    Publication date: December 24, 2020
    Inventors: Chun-Chieh Chiu, Pin-Hong Chen, Yi-Wei Chen, Tsun-Min Cheng, Chih-Chien Liu, Tzu-Chieh Chen, Chih-Chieh Tsai, Kai-Jiun Chang, Yi-An Huang, Chia-Chen Wu, Tzu-Hao Liu