Abstract: A method includes forming a transistor, which includes forming a gate dielectric on a semiconductor region, forming a gate electrode over the gate dielectric, and forming a source/drain region extending into the semiconductor region. The method further includes forming a source/drain contact plug over and electrically coupling to the source/drain region, and forming a gate contact plug over and in contact with the gate electrode. At least one of the forming the gate electrode, the forming the source/drain contact plug, and the forming the gate contact plug includes forming a metal nitride barrier layer, and depositing a metal-containing layer over and in contact with the metal nitride barrier layer. The metal-containing layer includes at least one of a cobalt layer and a metal silicide layer.

Abstract: A method includes etching a semiconductor substrate to form a first trench and a second trench. A remaining portion of the semiconductor substrate is left between the first trench and the second trench as a semiconductor region. A doped dielectric layer is formed on sidewalls of the semiconductor region and over a top surface of the semiconductor region. The doped dielectric layer includes a dopant. The first trench and the second trench are filled with a dielectric material. An anneal is then performed, and a p-type dopant or an n-type dopant in the doped dielectric layer is diffused into the semiconductor region to form a diffused semiconductor region.

Abstract: A method includes forming a bottom source/drain contact plug in a bottom inter-layer dielectric. The bottom source/drain contact plug is electrically coupled to a source/drain region of a transistor. The method further includes forming an inter-layer dielectric overlying the bottom source/drain contact plug. A source/drain contact opening is formed in the inter-layer dielectric, with the bottom source/drain contact plug exposed through the source/drain contact opening. A dielectric spacer layer is formed to have a first portion extending into the source/drain contact opening and a second portion over the inter-layer dielectric. An anisotropic etching is performed on the dielectric spacer layer, and a remaining vertical portion of the dielectric spacer layer forms a source/drain contact spacer. The remaining portion of the source/drain contact opening is filled to form an upper source/drain contact plug.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a recess in a layer. The recess has two opposite first inner walls and two opposite second inner walls, the first inner walls are spaced apart by a first distance, the second inner walls are spaced apart by a second distance, and the first distance is less than the second distance. The method includes depositing a first covering layer in the recess. The first covering layer covering the first inner walls is thinner than the first covering layer covering the second inner walls. The method includes removing the first covering layer over the first inner walls and a bottom surface of the recess.

Abstract: A plasma processing apparatus is provided. The apparatus includes a lower sheltering module. The apparatus further includes an upper sheltering module arranged adjacent to the lower sheltering module. The apparatus includes an upper plate and an upper PEZ ring positioned around the upper plate. The apparatus also includes a shadowing unit that includes a number of engaging parts in the form of arcs detachably positioned on the upper PEZ ring. In addition, the apparatus includes a plasma generation module for generating plasma in the peripheral region of the lower sheltering module and the upper sheltering module.

Abstract: An apparatus includes a first source and a common drain and on opposite sides of a first gate surrounded by a first gate spacer, a second source and the common drain on opposite sides of a second gate surrounded by a second gate spacer, a first protection layer formed along a sidewall of the first gate spacer, wherein a top surface of the first protection layer has a first slope, a second protection layer formed along a sidewall of the second gate spacer, wherein a top surface of the second protection layer has a second slope, a lower drain contact between the first gate and the second gate and an upper drain contact over the lower drain contact and between the first gate and the second gate, wherein at least a portion of the upper drain contact is in contact with the first slope and the second slope.

Abstract: An integrated circuit structure includes a semiconductor substrate having a plurality of semiconductor strips, a first recess being formed by two adjacent semiconductor strips among the plurality of semiconductor strips, a second recess being formed within the first recess, and an isolation region being provided in the first recess and the second recess. The second recess has a lower depth than the first recess.

Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin in a substrate, the first semiconductor fin adjacent the second semiconductor fin, forming a dummy gate structure extending over the first semiconductor fin and the second semiconductor fin, depositing a first dielectric material surrounding the dummy gate structure, replacing the dummy gate structure with a first metal gate structure, performing an etching process on the first metal gate structure and on the first dielectric material to form a first recess in the first metal gate structure and a second recess in the first dielectric material, wherein the first recess extends into the substrate, and wherein the second recess is disposed between the first semiconductor fin and the second semiconductor fin, and depositing a second dielectric material within the first recess.

Abstract: A semiconductor manufacturing method and semiconductor manufacturing tool for performing the same are disclosed. The semiconductor manufacturing tool includes a plasma chamber, a mounting platform disposed within the plasma chamber, a focus ring disposed within the plasma chamber, and at least one actuator mechanically coupled to the focus ring and configured to move the focus ring vertically. The actuator is configured to move the focus ring vertically when a plasma is present in the plasma chamber.

Abstract: A device includes a substrate, a first dielectric layer over the substrate, a first conductive feature in the first dielectric layer, and an etch stop layer over the first dielectric layer. The etch stop layer includes metal-doped aluminum nitride. The device further includes a second dielectric layer over the etch stop layer, and a second conductive feature in the second dielectric layer. The second conductive feature extends into the etch stop layer and contacts the first conductive feature.

Abstract: A finFET device and a method of forming are provided. The device includes a transistor comprising a gate electrode and a first source/drain region next to the gate electrode, the gate electrode being disposed over a first substrate. The device also includes a first dielectric layer extending along the first source/drain region, and a second dielectric layer overlying the first dielectric layer. The device also includes a contact disposed in the first dielectric layer and in the second dielectric layer, the contact contacting the gate electrode and the first source/drain region. A first portion of the first dielectric layer extends between the contact and the gate electrode. The contact extends along a sidewall of the first portion of the first dielectric layer and a first surface of the first portion of the first dielectric layer, the first surface of the first portion being farthest from the first substrate.

Abstract: Certain aspects direct to systems and methods for device or vendor independent network switch management on a management controller. The management controller is communicatively connected to a network switch through a Simple Network Management Protocol (SNMP) interface. The management controller receives parsed information of a management information base (MIB) file corresponding to the network switch, and establishes a communication between the management controller and the network switch through the SNMP interface based on the parsed information of the MIB file, in which the management controller functions as a client and the network switch functions as a server of the communication. Then the management controller receives an input to manage and configure the network switch, and manages and configures the network switch via the communication through the SNMP interface based on the input and the parsed information of the MIB file.

Abstract: A method of manufacturing a semiconductor device includes forming a semiconductor strip protruding above a substrate, forming isolation regions on opposing sides of the semiconductor strip, recessing the isolation regions in a first chamber using a first etching process, and increasing a planarity of the isolation regions in the first chamber using a second etching process.

Abstract: A method includes forming a transistor, which includes forming a gate dielectric on a semiconductor region, forming a gate electrode over the gate dielectric, and forming a source/drain region extending into the semiconductor region. The method further includes forming a source/drain contact plug over and electrically coupling to the source/drain region, and forming a gate contact plug over and in contact with the gate electrode. At least one of the forming the gate electrode, the forming the source/drain contact plug, and the forming the gate contact plug includes forming a metal nitride barrier layer, and depositing a metal-containing layer over and in contact with the metal nitride barrier layer. The metal-containing layer includes at least one of a cobalt layer and a metal silicide layer.

Abstract: A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.

Abstract: A method includes forming a bottom source/drain contact plug in a bottom inter-layer dielectric. The bottom source/drain contact plug is electrically coupled to a source/drain region of a transistor. The method further includes forming an inter-layer dielectric overlying the bottom source/drain contact plug. A source/drain contact opening is formed in the inter-layer dielectric, with the bottom source/drain contact plug exposed through the source/drain contact opening. A dielectric spacer layer is formed to have a first portion extending into the source/drain contact opening and a second portion over the inter-layer dielectric. An anisotropic etching is performed on the dielectric spacer layer, and a remaining vertical portion of the dielectric spacer layer forms a source/drain contact spacer. The remaining portion of the source/drain contact opening is filled to form an upper source/drain contact plug.

Abstract: A method for forming semiconductor device structure is provided. The method includes forming a gate stack over a semiconductor substrate and forming a spacer element over a sidewall of the gate stack. The method also includes forming a dielectric layer over the semiconductor substrate to surround the gate stack and the spacer element and replacing the gate stack with a metal gate stack. The method further includes forming a protection element over the metal gate stack and forming a conductive contact partially surrounded by the dielectric layer. A portion of the conductive contact is formed directly above a portion of the protection element.

Abstract: An interconnect structure and a method of forming are provided. The method includes forming an opening in a dielectric layer and an etch stop layer, wherein the opening extends only partially through the etch stop layer. The method also includes creating a vacuum environment around the device. After creating the vacuum environment around the device, the method includes etching through the etch stop layer to extend the opening and expose a first conductive feature. The method also includes forming a second conductive feature in the opening.

Abstract: A method of forming a semiconductor device includes forming a source/drain region on a substrate and forming a first interlayer dielectric (ILD) layer over the source/drain region. The method further includes forming a second ILD layer over the first ILD layer, forming a source/drain contact structure within the first ILD layer and the second ILD layer, and selectively removing a portion of the source/drain contact structure to form a concave top surface of the source/drain contact structure.

Abstract: An apparatus includes a first source and a common drain and on opposite sides of a first gate surrounded by a first gate spacer, a second source and the common drain on opposite sides of a second gate surrounded by a second gate spacer, a first protection layer formed along a sidewall of the first gate spacer, wherein a top surface of the first protection layer has a first slope, a second protection layer formed along a sidewall of the second gate spacer, wherein a top surface of the second protection layer has a second slope, a lower drain contact between the first gate and the second gate and an upper drain contact over the lower drain contact and between the first gate and the second gate, wherein at least a portion of the upper drain contact is in contact with the first slope and the second slope.