Abstract: Provided a separator, a preparation method thereof, and a secondary battery, a battery module, a battery pack, and an electric apparatus containing such separator. The separator includes: a substrate and a coating applied on at least one surface of the substrate, where the coating includes 40 wt % to 90 wt % first organic particles, 2 wt % to 15 wt % pressure-sensitive binder, and optionally 0 wt % to 50 wt % second organic particles. The first organic particles include an organic polymer and an inorganic substance. The pressure-sensitive binder includes an organic polymer and a plasticizer. The separator has good ionic conductivity and adhesion performance at room temperature, is not adhered under a pressure of 1 MPa or below and is significantly adhered under a pressure of 2 MPa or above, which can significantly improve structural stability and ionic conductivity of an electrochemical device while satisfying requirements for yield rate of production and kinetic performance of a battery cell.

Abstract: A mechanism for building decentralized computer applications that execute on a distributed computing system. The present technology works within a web browser, client application, or other software and provides access to decentralized computer applications through the browser. The present technology is non-custodial, wherein a public-private key pair, which represents user identity, is created on a client machine and then directly encrypted by a third-party platform without relying on one centralized computing system.

Abstract: In some embodiments, the present disclosure relates an integrated chip including a substrate. A conductive interconnect feature is arranged over the substrate. The conductive interconnect feature has a base feature portion with a base feature width and an upper feature portion with an upper feature width. The upper feature width is narrower than the base feature width such that the conductive interconnect feature has tapered outer feature sidewalls. An interconnect via is arranged over the conductive interconnect feature. The interconnect via has a base via portion with a base via width and an upper via portion with an upper via width. The upper via width is wider than the base via width such that the interconnect via has tapered outer via sidewalls.

Abstract: An antenna module includes a first metal plate and a frame body. The frame body surrounds the first metal plate. The frame body includes a first antenna radiator, a second antenna radiator, a third antenna radiator, a first breakpoint and a second breakpoint. The first antenna radiator includes a first feeding end and excites a first frequency band. The second antenna radiator includes a second feeding end and excites a second frequency band. The third antenna radiator includes a third feeding end and excites a third frequency band. The first breakpoint is located between the first antenna radiator and the second antenna radiator. The second breakpoint is located between the second antenna radiator and the third antenna radiator. An electronic device including the above-mentioned antenna module is also provided.

Abstract: A semiconductor chip includes a first intellectual property block. There are a second intellectual property block and a third intellectual property block around the first intellectual property block. There is a multiple metal layer stack over the first intellectual property block, the second intellectual property block, and the third intellectual property block. An interconnect structure is situated in the upper portion of the multiple metal layer stack. The interconnect structure is configured for connecting the first intellectual property block and the second intellectual property block. In addition, at least a part of the interconnect structure extends across and over the third intellectual property block.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure, the method includes forming a buffer layer over a substrate. An active layer is formed on the buffer layer. A top electrode is formed on the active layer. An etch process is performed on the buffer layer and the substrate to define a plurality of pillar structures. The plurality of pillar structures include a first pillar structure laterally offset from a second pillar structure. At least portions of the first and second pillar structures are spaced laterally between sidewalls of the top electrode.

Abstract: In a method of manufacturing a semiconductor device, a fin structure having a channel region protruding from an isolation insulating layer disposed over a semiconductor substrate is formed, a cleaning operation is performed, and an epitaxial semiconductor layer is formed over the channel region. The cleaning operation and the forming the epitaxial semiconductor layer are performed in a same chamber without breaking vacuum.

Abstract: Embodiments of the present technology include semiconductor processing methods. The methods may include providing a silicon-containing precursor and a dopant precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the semiconductor processing chamber. A silicon-containing material may be formed on the substrate. The methods may include contacting the silicon-containing material with the silicon-containing precursor and the dopant precursor. The methods may include forming a doped silicon-containing material on the silicon-containing material. The methods may include oxidizing the substrate. The oxidizing may form an oxidized doped silicon-containing material. The methods may include etching the oxidized doped silicon-containing material.

Abstract: A flyback power converter includes a power transformer, a first lossless voltage conversion circuit, a first low-dropout linear regulator and a secondary side power supply circuit. The first low-dropout linear regulator (LDO) generates a first operation voltage as power supply for being supplied to a sub-operation circuit. The secondary side power supply circuit includes a second lossless voltage conversion circuit and a second LDO. The second LDO generates a second operation voltage. The first operation voltage and the second operation voltage are shunted to a common node. When a first lossless conversion voltage is greater than a first threshold voltage, the second LDO is enabled to generate the second operation voltage to replace the first operation voltage as power supply supplied to the sub-operation circuit; wherein the second lossless conversion voltage is lower than the first lossless switching voltage.

Abstract: Aspects of the present disclosure relate to wireless communications, and more particularly, to techniques for allowing for the coexistence of legacy and non-legacy PUCCH formats. An example method generally includes generating a first orthogonal sequence for a first payload for a physical uplink control channel (PUCCH) to be transmitted; generating a second orthogonal sequence for a second payload for the PUCCH to be transmitted; mapping the first orthogonal sequence to a first set of virtual resources and the second orthogonal sequence to a second set of virtual resources; mapping the first set of virtual resources to a first set of physical resources and the second set of virtual resources to a second set of physical resources; and transmitting the first and second payloads for the PUCCH on the first and second sets of physical resources.

Abstract: An array substrate includes a first pixel driving circuit, a second pixel driving circuit, and a third pixel driving circuit; and a first voltage supply line, a second voltage supply line, and a third voltage supply line configured to provide a constant voltage signal respectively to the first pixel driving circuit, the second pixel driving circuit, and the third pixel driving circuit. The first voltage signal line crosses over a second capacitor electrode in the first pixel driving circuit by a first overlapping area. The second voltage supply line crosses over a second capacitor electrode in the second pixel driving circuit by a second overlapping area. The third voltage supply line crosses over a second capacitor electrode in the third pixel driving circuit by a third overlapping area. The third overlapping area is greater than the first overlapping area, and is greater than the second overlapping area.

Abstract: Present invention is related to a tumor microenvironment on chip or a biochip for cell therapy having a carrier, a first cell or tissue culture area and a second cell or tissue area imbedded within the carrier. The present invention provides a biochip successfully cooperating micro fluidic technology and cell culture achieving the goal for detecting or testing the function of cell therapy for cancer or tumor.

Abstract: Methods, systems, and devices for wireless communications are described. A first user equipment (UE) may receive, from a base station, control signaling indicating a set of resources of a sidelink channel available for sidelink communication with a second UE. The first UE may receive a sidelink preemption indication indicating that at least a first resource from the set of resources is preempted. The first UE may communicate a sidelink transmission over the sidelink channel with the second UE based on the sidelink preemption indication. In some cases, the first UE may determine whether the SPI satisfies one or more thresholds and the first UE may communicate the sidelink transmission, or refrain from communicating the sidelink transmission, based on determining whether the SPI satisfies the one or more thresholds.

Abstract: Methods, systems, computer program products for determining the source of activity during interaction with a user interface are provided. The method comprises selecting one or more input devices from a plurality of available input devices coupled to the user interface and receiving respective measurements for the selected one or more input devices. Based on the received respective measurements, respective feature vectors for the one or more input devices are generated and then inputted to a pre-defined regression model. Then, the source of activity is determined based on a result received from the regression model.

Abstract: In one embodiment, a method includes receiving a first network event corresponding to a first transaction, the first network event being assigned a unique transaction group identifier, authorizing the first transaction based on a balance value of a ledger account recorded in an account ledger, recording a first update in the account ledger, comprising recording the unique transaction group identifier in association with the first update and the ledger account and modifying the balance value of the ledger account, receiving a second network event corresponding to a second transaction, determining that a unique transaction group identifier assigned to the second network event matches the unique transaction group identifier associated with the first update and the ledger account, and recording a second update in the account ledger, comprising recording the unique transaction group identifier in association with the second update without modifying the balance value of the ledger account.

Abstract: Implementations of this specification provide methods and apparatuses for generating index entries. One method includes: acquiring a first sequence number of front large object data that is adjacent to a target data to be inserted in a large object data, wherein the first sequence number is generated based on a first code arrangement sequence and is comprised in a first index entry corresponding to the front large object data, in response to determining that the second sequence number immediately following the first sequence number is occupied, determining, based on a second code arrangement sequence, a branch index sequence number for the target data, and adding an index entry comprising the branch index sequence number to an index of the large object data, wherein the index entry is added between the first index entry comprising the first sequence number and a second index entry comprising the second sequence number.

Abstract: The embodiments of the present disclosure disclose a method for uplink multiuser data transmission and a system for uplink multiuser multiple input multiple output. The method includes: sending, by an access point AP, indication information to at least two stations STAs, wherein the indication information is used for indicating that the at least two STAs perform an uplink multiuser data transmission; receiving, by the AP, uplink data sent by the at least two STAs through channels from the at least two STAs to the AP, respectively; and demodulating, by the AP, the uplink data sent by the at least two STAs using receiving beams corresponding to pre-estimated channels from the at least two STAs to the AP, respectively.

Abstract: A mechanism for building decentralized computer applications that execute on a distributed computing system. The present technology works within a web browser, client application, or other software and provides access to decentralized computer applications through the browser. The present technology is non-custodial, wherein a public-private key pair, which represents user identity, is created on a client machine and then directly encrypted by a third-party platform without relying on one centralized computing system.

Abstract: A multilayer structure, a capacitor structure and an electronic device are provided. The multilayer structure includes a first dielectric layer, a second dielectric layer and an intermediate dielectric layer. The intermediate dielectric layer is disposed between the first dielectric layer and the second dielectric layer. A material of the intermediate dielectric layer is represented by a formula of AxB1-xO, wherein A includes hafnium (Hf), zirconium (Zr), lanthanum (La) or tantalum (Ta), B includes lanthanum (La), aluminum (Al) or tantalum (Ta), A is different from B, O is oxygen, and x is a number less than 1 and greater than 0.

Abstract: A sweep voltage generator and a display panel are provided. The sweep voltage generator includes an output node, a current generating block and a voltage regulating block. The output node is used to provide a sweep signal. The current generating block is coupled to the output node, includes a detection path for detecting an output load variation on the output node, and adjusts the sweep signal provided by the output node based on the output load variation. The voltage regulating block is coupled to the output node for regulating a voltage of the output node.