Patents by Inventor Yibin Ye

Yibin Ye has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Two transistor gain cell, method, and system
    Patent number: 7120072
    Abstract: A two transistor memory cell includes a write transistor and a read transistor. When reading the memory cell, the read transistor is turned on, and a voltage develops on a read bit line.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: October 10, 2006
    Assignee: Intel Corporation
    Inventors: Yibin Ye, Dinesh Somasekhar, Muhammad M Khellah, Fabrice Paillet, Stephen H Tang, Ali Keshavarzi, Shih-Lien L Lu, Vivek K De
  • Method and apparatus for reducing power consumption through dynamic control of supply voltage and body bias including maintaining a substantially constant operating frequency
    Patent number: 7120804
    Abstract: An approach for power reduction of an integrated circuit device. In response to detecting a change in an activity factor associated with an integrated circuit device from a first activity factor to a second activity factor, a supply voltage and a body bias associated with the integrated circuit device are adjusted based on the second activity factor to reduce power consumption. For one aspect, the supply voltage and body bias are adjusted to maintain a substantially constant operating frequency for the integrated circuit device.
    Type: Grant
    Filed: December 23, 2002
    Date of Patent: October 10, 2006
    Assignee: Intel Corporation
    Inventors: James W. Tschanz, Yibin Ye, Liqiong Wei, Vivek K. De
  • Crosspoint memory array utilizing one time programmable antifuse cells
    Patent number: 7110278
    Abstract: Crosspoint memory arrays utilizing one time programmable antifuse cells are disclosed.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: September 19, 2006
    Assignee: Intel Corporation
    Inventors: Ali Keshavarzi, Fabrice Paillet, Muhammad M. Khellah, Dinesh Somasekhar, Yibin Ye, Stephen H. Tang, Mohsen Alavi, Vivek K. De
  • OTP antifuse cell and cell array
    Patent number: 7102951
    Abstract: Different embodiments of a one-time-programmable antifuse cell included. In one embodiment, a circuit is provided that includes an antifuse element, a high voltage device, and a sense circuit. The antifuse element has a voltage supply terminal to be at a sense voltage during sensing/reading and a higher programming voltage during programming. The sense circuit is configured to enable programming the antifuse element during programming and to sense the state of the antifuse element during sensing. The high voltage device is coupled between the antifuse element and the sense circuit to couple the antifuse element to the sense circuit during programming and sensing and to protectively shield the sense circuit from the higher programming voltage during programming.
    Type: Grant
    Filed: November 1, 2004
    Date of Patent: September 5, 2006
    Assignee: Intel Corporation
    Inventors: Fabrice Paillet, Ali Keshavarzi, Muhammad M. Khellah, Dinesh Somasekhar, Yibin Ye, Stephen H. Tang, Mohsen Alavi, Vivek K. De
  • Overvoltage detection apparatus, method, and system
    Patent number: 7102358
    Abstract: A transistor may have degraded characteristics because of an overvoltage condition. The degraded characteristics may be sensed to determine that the transistor has previously been subjected to an overvoltage condition.
    Type: Grant
    Filed: June 29, 2004
    Date of Patent: September 5, 2006
    Assignee: Intel Corporation
    Inventors: Ali Keshavarzi, Fabrice Paillet, Muhammad M Khellah, Dinesh Somasekhar, Yibin Ye, Stephen H Tang, Mohsen Alavi, Vivek K De
  • Floating-body dynamic random access memory and method of fabrication in tri-gate technology
    Patent number: 7098507
    Abstract: A floating-body dynamic random access memory device may include a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer may be formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode may be formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. The gate electrode may only partially deplete a region of the semiconductor body, and the partially depleted region may be used as a storage node for logic states.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: August 29, 2006
    Assignee: Intel Corporation
    Inventors: Stephen H. Tang, Ali Keshavarzi, Dinesh Somasekhar, Fabrice Paillet, Muhammad M. Khellah, Yibin Ye, Shih-Lien L. Lu, Brian Doyle, Suman Datta, Vivek K. De
  • 2-Transistor floating-body dram
    Publication number: 20060187706
    Abstract: A dynamic random access memory includes a cell having a circuit between a floating-body transistor and a bit line. Activation of the circuit is controlled to provide isolation between the floating body and bit-line voltage both during write operations and during times when the cell is unselected. The added isolation improves performance, for example, by reducing the need for gate-to-body coupling and the magnitude of voltage swings between the bit lines.
    Type: Application
    Filed: February 22, 2005
    Publication date: August 24, 2006
    Inventors: Stephen Tang, Ali Keshavarzi, Dinesh Somasekhar, Fabrice Paillet, Muhammad Khellah, Yibin Ye, Shih-Lien Lu, Vivek De
  • Representative majority voter for bus invert coding
    Publication number: 20060184595
    Abstract: In general, in one aspect, the disclosure describes an apparatus inluding a representative majority voter gate to analyze bit transitions of a pluraility of bits. The plurailuty of bits are analzed in groups. The representative majority voter gate generates an invert signal based on the analysis. The apparatus further inludes a conditional inverter to apply the invert signal to the pluraility of bits.
    Type: Application
    Filed: February 16, 2005
    Publication date: August 17, 2006
    Inventors: James Tschanz, Mircea Stan, Muhammad Khellah, Yibin Ye, Vivek De
  • Apparatus and method for a one-phase write to a one-transistor memory cell array
    Patent number: 7075821
    Abstract: A method and apparatus for a one-phase write to a one-transistor memory cell array. In one embodiment, the method includes a one-phase write to a selected wordline of a memory cell array. Once the wordline is selected, a logical zero value is stored within at least one memory cell of the selected wordline of the memory cell array. Simultaneously, a logical 0 value is stored within at least one memory cell of the selected wordline of the selected memory cell array. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: July 11, 2006
    Assignee: Intel Corporation
    Inventors: Yibin Ye, Stephen H. Tang, Ali Keshavarzi, Dinesh Somasekhar, Fabrice Paillet, Muhammad M. Khellah, Gerhard Schrom, Vivek K. De
  • Floating-body DRAM with two-phase write
    Patent number: 7072205
    Abstract: A row of floating-body single transistor memory cells is written to in two phases.
    Type: Grant
    Filed: November 19, 2003
    Date of Patent: July 4, 2006
    Assignee: Intel Corporation
    Inventors: Stephen H. Tang, Ali Keshavarzi, Dinesh Somasekhar, Fabrice Paillet, Muhammad M. Khellah, Yibin Ye, Shih-Lien L. Lu, Vivek K. De
  • One time programmable memory
    Publication number: 20060139995
    Abstract: A one time programmable memory includes isolated gate transistors that may be programmed by subjecting the isolated gate transistors to voltage conditions that degrade characteristics of the isolated gate transistors. The degraded characteristics may be sensed to read the memory.
    Type: Application
    Filed: December 28, 2004
    Publication date: June 29, 2006
    Inventors: Ali Keshavarzi, Fabrice Paillet, Muhammad Khellah, Dinesh Somasekhar, Yibin Ye, Stephen Tang, Mohsen Alavi, Vivek De
  • Floating-body memory cell write
    Patent number: 7061806
    Abstract: A system to write to a plurality of memory cells coupled to a word line, each of the plurality of memory cells comprising a transistor having a source, a drain, a body and a gate coupled to the word line. Some embodiments provide biasing of one or more of the plurality of memory cells in saturation to inject charge carriers into the body of the one or more of the plurality of memory cells, and biasing of each of the plurality of memory cells in accumulation to tunnel charge carriers from the body of each of the plurality of memory cells to the gate of each of the plurality of memory cells.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: June 13, 2006
    Assignee: Intel Corporation
    Inventors: Stephen H. Tang, Ali Keshavarzi, Dinesh Somasekhar, Fabrice Paillet, Muhammad M. Khellah, Yibin Ye, Shih-Lien L. Lu, Vivek K. De
  • Floating-body dynamic random access memory with purge line
    Patent number: 7057927
    Abstract: Embodiments relate to a Floating Body Dynamic Random Access Memory (FBDRAM). The FBDRAM utilizes a purge line to reset a FBDRAM cell, prior to writing data to the FBDRAM cell.
    Type: Grant
    Filed: November 30, 2005
    Date of Patent: June 6, 2006
    Assignee: Intel Corporation
    Inventors: Stephen H. Tang, Ali Keshavarzi, Dinesh Somasekhar, Fabrice Paillet, Muhammad M. Khellah, Yibin Ye, Shih-Lien Lu, Vivek K. De
  • Memory circuit
    Publication number: 20060114711
    Abstract: In one embodiment, a memory array is provided comprising one or more columns each comprising a plurality of bit cells divided into groups of bit cells with each group of bit cells controllably coupled to a separate bit line.
    Type: Application
    Filed: December 1, 2004
    Publication date: June 1, 2006
    Inventors: Muhammad Khellah, Dinesh Somasekhar, Yibin Ye, Gunjan Pandya, Vivek De
  • Single-stage and multi-stage low power interconnect architectures
    Publication number: 20060109028
    Abstract: An interconnect architecture is provided to reduce power consumption. A first driver may drive signals on a first interconnect and a second driver may drive signals on a second interconnect. The first driver may be powered by a first voltage and the second driver may be powered by a second voltage different than the first voltage.
    Type: Application
    Filed: December 22, 2005
    Publication date: May 25, 2006
    Inventors: Maged Ghoneima, Peter Caputa, Muhammad Khellah, Ram Krishnamurthy, James Tschanz, Yibin Ye, Vivek De, Yehia Ismail
  • Method and apparatus to clamp SRAM supply voltage
    Publication number: 20060104128
    Abstract: An apparatus and method are provided for limiting a drop of a supply voltage in an SRAM device to retain the state of the memory during an IDLE state. The apparatus may include a memory array, a sleep device, and a clamping circuit. The clamping circuit may be configured to activate the sleep device when a voltage drop across the memory array falls below a preset voltage and the memory array is in an IDLE state.
    Type: Application
    Filed: December 30, 2005
    Publication date: May 18, 2006
    Inventors: Dinesh Somasekhar, Muhammad Khellah, Yibin Ye, Vivek De, James Tschanz, Stephen Tang
  • Floating-body dynamic random access memory with purge line
    Publication number: 20060098482
    Abstract: Embodiments relate to a Floating Body Dynamic Random Access Memory (FBDRAM). The FBDRAM utilizes a purge line to reset a FBDRAM cell, prior to writing data to the FBDRAM cell.
    Type: Application
    Filed: November 30, 2005
    Publication date: May 11, 2006
    Inventors: Stephen Tang, Ali Keshavarzi, Dinesh Somasekhar, Fabrice Paillet, Muhammad Khellah, Yibin Ye, Shih-Lien Lu, Vivek De
  • OTP antifuse cell and cell array
    Publication number: 20060092742
    Abstract: Different embodiments of a one-time-programmable antifuse cell are provided in this disclosure. In one embodiment, a circuit is provided that includes an antifuse element, a high voltage device, and a sense circuit. The antifuse element has a voltage supply terminal to be at a sense voltage during sensing/reading and a higher programming voltage during programming. The sense circuit is configured to enable programming the antifuse element during programming and to sense the state of the antifuse element during sensing. The high voltage device is coupled between the antifuse element and the sense circuit to couple the antifuse element to the sense circuit during programming and sensing and to protectively shield the sense circuit from the higher programming voltage during programming.
    Type: Application
    Filed: November 1, 2004
    Publication date: May 4, 2006
    Inventors: Fabrice Paillet, Ali Keshavarzi, Muhammad Khellah, Dinesh Somasekhar, Yibin Ye, Stephen Tang, Mohsen Alavi, Vivek De
  • Floating-body DRAM using write word line for increased retention time
    Patent number: 7031203
    Abstract: A DRAM memory cell uses a single transistor to perform the data storage and switching functions of a conventional cell. The transistor has a floating channel body which stores a potential that corresponds to one of two digital data values. The transistor further includes a gate connected to a first word line, a drain connected to a second word line, and a source connected to a bit line. By setting the word and bit lines to specific voltage states, the channel body stores a digital one potential as a result of impact ionization and a digital zero value as a result of forward bias of body-to-source junction.
    Type: Grant
    Filed: February 28, 2005
    Date of Patent: April 18, 2006
    Assignee: Intel Corporation
    Inventors: Stephen Tang, Ali Keshavarzi, Dinesh Somasekhar, Fabrice Paillet, Muhammad Khellah, Yibin Ye, Vivek De
  • Non volatile data storage through dielectric breakdown
    Publication number: 20060071646
    Abstract: A method is described that induced dielectric breakdown within a capacitor's dielectric material while driving a current through the capacitor. The current is specific to data that is being written into the capacitor. The method also involves reading the data by interpreting behavior of the capacitor that is determined by the capacitor's resistance, where, the capacitor's resistance is a consequence of the inducing and the driving.
    Type: Application
    Filed: September 30, 2004
    Publication date: April 6, 2006
    Inventors: Fabrice Paillet, Ali Keshavarzi, Muhammad Khellah, Dinesh Somasekhar, Yibin Ye, Stephen Tang, Alavi Mohsen, Vivek De