Patents by Inventor Yibo Yan

Yibo Yan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240105193
    Abstract: This application provides picture or audio encoding and decoding methods and apparatuses, and relates to the field of artificial intelligence (AI)—based picture or audio encoding and decoding technologies, and specifically, to the field of neural network-based picture feature map or audio feature variable encoding and decoding technologies. The encoding method includes: obtaining a to-be-encoded target, where the to-be-encoded target includes a plurality of feature elements, and the plurality of feature elements include a first feature element. The method further includes: obtaining a probability estimation result of the first feature element; determining, based on the probability estimation result of the first feature element, whether to perform entropy encoding on the first feature element; and performing entropy encoding on the first feature element only when it is determined that entropy encoding needs to be performed on the first feature element.
    Type: Application
    Filed: December 1, 2023
    Publication date: March 28, 2024
    Inventors: Jue Mao, Yin Zhao, Ning Yan, Haitao Yang, Lian Zhang, Jing Wang, Yibo Shi
  • Patent number: 11922986
    Abstract: The present invention relates to a kind of magnetic heterojunction structure and the method of controlling and achieving spin logic and multiple-state storage functions. The said single magnetic heterojunction structure comprises the substrate, in-plane anti-ferromagnetic layer, in-plane ferromagnetic layer, nonmagnetic layer, vertical ferromagnetic layer, and vertical anti-ferromagnetic layer respectively from the bottom up; the said in-plane ferromagnetic layer and the said vertical ferromagnetic layer are coupled together through the said nonmagnetic layer in the middle; in-plane exchange biases, namely exchange biases in the plane, exist between the said in-plane ferromagnetic layer and the said in-plane anti-ferromagnetic layer, and out-of-plane exchange biases, namely exchange biases out of the plane, exist between the said vertical ferromagnetic layer and the said vertical anti-ferromagnetic layer.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: March 5, 2024
    Assignee: SHAN DONG UNIVERSITY
    Inventors: Shishen Yan, Yufeng Tian, Lihui Bai, Yibo Fan, Xiang Han
  • Patent number: 9024456
    Abstract: A photolithography alignment mark and a mask and semiconductor wafer containing said mark are described. The alignment mark comprises: a plurality of first alignment lines arranged parallel with each other in a first direction; a plurality of second alignment lines arranged parallel with each other in a second direction perpendicular to the first direction, and wherein each of the plurality of first alignment lines is composed of a predetermined number of first fine alignment lines uniformly spaced from each other, and each of the plurality of second alignment lines is composed of a predetermined number of second fine alignment lines uniformly spaced from each other. Alignment marks can be located in non-circuit pattern regions of the mask and on a plurality of layers in mark regions on the wafer.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: May 5, 2015
    Assignee: Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Xiaosong Yang, Yibo Yan, Tzu Hsuan Lu
  • Publication number: 20130075938
    Abstract: A photolithography alignment mark and a mask and semiconductor wafer containing said mark are described. The alignment mark comprises: a plurality of first alignment lines arranged parallel with each other in a first direction; a plurality of second alignment lines arranged parallel with each other in a second direction perpendicular to the first direction, and wherein each of the plurality of first alignment lines is composed of a predetermined number of first fine alignment lines uniformly spaced from each other, and each of the plurality of second alignment lines is composed of a predetermined number of second fine alignment lines uniformly spaced from each other. Alignment marks can be located in non-circuit pattern regions of the mask and on a plurality of layers in mark regions on the wafer.
    Type: Application
    Filed: December 16, 2011
    Publication date: March 28, 2013
    Applicant: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: XIAOSONG YANG, Yibo Yan, Tzu Hsuan Lu