Abstract: In one embodiment, a memory apparatus is provided with at least one local bit-line; a precharge control circuit, coupled to the at least one local bit-line, and adapted to be operable to initiate a precharge pulse after the at least one local bit-line is discharged and to terminate the precharge pulse after the at least one local bit-line has been precharged; a precharge pull-up device, coupled to the precharge control circuit, a first voltage source, and the at least one local bit-line, and adapted to be operable to connect the first voltage source to the at least one local bit-line during the precharge pulse to precharge the at least one local bit-line; and a selected one of a plurality of evaluation pull-down devices, coupled to a clock source, a second voltage source, and the at least one bit-line, and adapted to be operable to couple the at least one local bit-line to the second voltage source during the clock signal pulse to discharge the at least one local bit-line.

Abstract: In one embodiment, a memory apparatus is provided with at least one local bit-line; a precharge control circuit, coupled to the at least one local bit-line, and adapted to be operable to initiate a precharge pulse after the at least one local bit-line is discharged and to terminate the precharge pulse after the at least one local bit-line has been precharged; a precharge pull-up device, coupled to the precharge control circuit, a first voltage source, and the at least one local bit-line, and adapted to be operable to connect the first voltage source to the at least one local bit-line during the precharge pulse to precharge the at least one local bit-line; and a selected one of a plurality of evaluation pull-down devices, coupled to a clock source, a second voltage source, and the at least one bit-line, and adapted to be operable to couple the at least one local bit-line to the second voltage source during the clock signal pulse to discharge the at least one local bit-line.

Abstract: An apparatus and method for a pseudo-dynamic latch are disclosed. A deracer circuit includes a first logic gate configured to receive a data signal from a domino logic circuit and to invert the data signal. A second logic gate is configured to receive the inverted data signal and an inverted select signal and to generate a select signal. Thus, the deracer circuit is configured to prevent the select signal from being high when a precharge edge of a data signal arrives.

Abstract: An apparatus and method for a pseudo-dynamic latch are disclosed. A deracer circuit includes a first logic gate configured to receive a data signal from a domino logic circuit and to invert the data signal. A second logic gate is configured to receive the inverted data signal and an inverted select signal and to generate a select signal. Thus, the deracer circuit is configured to prevent the select signal from being high when a precharge edge of a data signal arrives.