Abstract: An embodiment of the present application provides a test method for tolerance against the hot carrier effect, applied to an I/O circuit of a memory, the I/O circuit having an output terminal, comprising: controlling the output terminal to alternately output a first level and a second level, the first level being higher than the second level; obtaining a degradation rate of an output performance parameter of the I/O circuit according to the first level and the second level; and obtaining tolerance of the I/O circuit against the hot carrier effect based on the degradation rate.

Abstract: In one embodiment, a process is performed during controlling Autonomous Driving Vehicle (ADV). A confidence level associated with a sensed obstacle is determined. If the confidence level is below a confidence threshold, and a distance between the ADV and a potential point of contact with the sensed obstacle is below a distance threshold, then performance of a driving decision is delayed. Otherwise, the driving decision is performed to reduce risk of contact with the sensed obstacle.

Abstract: An embodiment of the present application provides a test method for tolerance against the hot carrier effect, applied to an I/O circuit of a memory, the I/O circuit having an output terminal, comprising: controlling the output terminal to alternately output a first level and a second level, the first level being higher than the second level; obtaining a degradation rate of an output performance parameter of the I/O circuit according to the first level and the second level; and obtaining tolerance of the I/O circuit against the hot carrier effect based on the degradation rate.

Abstract: The present disclosure provides a test system and a test method. The test system includes: a signal providing module, configured to provide a first clock signal and a second clock signal for a to-be-tested memory, the to-be-tested memory executes a write command based on the first clock signal, so that the to-be-tested memory stores preset data, and the to-be-tested memory executes a read command based on the second clock signal, to read storage data stored in the to-be-tested memory; and one of the first clock signal and the second clock signal is a symmetrical clock signal, and the other is an asymmetrical clock signal with a preset duty cycle; and a processing module, configured to obtain the storage data, and obtain a clock signal tolerance of the to-be-tested memory according to a comparison result between the storage data and the preset data.

Abstract: The present disclosure provides a test system and a test method. The test system includes: a signal providing module, configured to provide a first clock signal and a second clock signal for a to-be-tested memory, the to-be-tested memory executes a write command based on the first clock signal, so that the to-be-tested memory stores preset data, and the to-be-tested memory executes a read command based on the second clock signal, to read storage data stored in the to-be-tested memory; and one of the first clock signal and the second clock signal is a symmetrical clock signal, and the other is an asymmetrical clock signal with a preset duty cycle; and a processing module, configured to obtain the storage data, and obtain a clock signal tolerance of the to-be-tested memory according to a comparison result between the storage data and the preset data.

Abstract: A node layout determining method and apparatus, a computing device, and a computer readable medium are disclosed. The node layout determining method comprises: laying out, for a node group comprising a plurality of nodes, the plurality of nodes in the node group according to a correspondence relationship among the nodes in the node group, to obtain relative coordinates of each of the plurality of nodes in the corresponding node group; determining a relationship among node groups according to the correspondence relationship among the nodes in a node database; laying out node groups in the node database according to the relationship among the node groups and numbers of nodes included in the node groups, to obtain group coordinates of each node group; and obtaining true coordinates of each node according to the relative coordinates of each node and the group coordinates of the node group to which the node belongs.

Abstract: A node layout determining method and apparatus, a computing device, and a computer readable medium are disclosed. The node layout determining method comprises: laying out, for a node group comprising a plurality of nodes, the plurality of nodes in the node group according to a correspondence relationship among the nodes in the node group, to obtain relative coordinates of each of the plurality of nodes in the corresponding node group; determining a relationship among node groups according to the correspondence relationship among the nodes in a node database; laying out node groups in the node database according to the relationship among the node groups and numbers of nodes included in the node groups, to obtain group coordinates of each node group; and obtaining true coordinates of each node according to the relative coordinates of each node and the group coordinates of the node group to which the node belongs.