Patents by Inventor Yih Chang

Yih Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7812420
    Abstract: An integrated circuit device for converting an incident optical signal into an electrical signal comprises a semiconductor substrate, a well region formed inside the semiconductor substrate, a dielectric layer formed over the well region, and a layer of polysilicon for receiving the incident optical signal, formed over the dielectric layer, including a p-type portion, an n-type portion and an undoped portion disposed between the p-type and n-type portions, wherein the well region is biased to control the layer of polysilicon for providing the electrical signal.
    Type: Grant
    Filed: October 2, 2006
    Date of Patent: October 12, 2010
    Inventors: Yu-Da Shiu, Chyh-Yih Chang, Ming-Dou Ker, Che-Hao Chuang
  • Patent number: 7554159
    Abstract: An electrostatic discharge protection device that includes a semiconductor substrate of a first dopant type, at least one source/drain pair of a second dopant type formed in the substrate, wherein the source/drain pair is separated to define a channel region therebetween, a lightly-doped region of the first dopant type defined between the source/drain pair and including at least a portion of the channel region, a gate dielectric layer formed over the substrate, and a gate formed over the gate dielectric layer and above the channel region.
    Type: Grant
    Filed: January 31, 2005
    Date of Patent: June 30, 2009
    Inventors: Ming-Dou Ker, Tang-Kui Tseng, Hsin-Chin Jiang, Chyh-Yih Chang, Jeng-Jie Peng
  • Publication number: 20090145877
    Abstract: A method for controlling an ADI-AEI CD difference ratio of openings having different sizes is described. The openings are formed through a silicon-containing material layer, an etching resistive layer and a target material layer in turn. Before the opening etching steps, at least one of the opening patterns in the photoresist mask is altered in size through photoresist trimming or deposition of a substantially conformal polymer layer. A first etching step forming thicker polymer on the sidewall of the wider opening pattern is performed to form a patterned Si-containing material layer. A second etching step is performed to remove exposed portions of the etching resistive layer and the target material layer. At least one parameter among the parameters of the photoresist trimming or polymer layer deposition step and the etching parameters of the first etching step is controlled to obtain a predetermined ADI-AEI CD difference ratio.
    Type: Application
    Filed: February 16, 2009
    Publication date: June 11, 2009
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Feng-Yih Chang, Pei-Yu Chou, Jiunn-Hsiung Liao, Chih-Wen Feng, Ying-Chih Lin
  • Publication number: 20090096022
    Abstract: An exemplary lateral diffused metal oxide semiconductor device includes a first-type substrate, a gate oxide film disposed on the first-type substrate, a poly gate disposed on the gate oxide film, a first second-type slightly doped region formed in the first-type substrate and acting as a well, a first first-type highly doped region formed in the well and acting as a body, a first second-type highly doped region formed in the body and acting as a source, a second second-type highly doped region formed in the well and acting as a drain, a second first-type highly doped region formed in the body, and a first fist-type doped region formed in the body and is beneath the source.
    Type: Application
    Filed: June 5, 2008
    Publication date: April 16, 2009
    Applicant: FITIPOWER INTEGRATED TECHNOLOGY, INC.
    Inventors: CHYH-YIH CHANG, HSING-HUA SUN, TSUAN-LUN LUNG, CHEN-MING CHIU
  • Patent number: 7511417
    Abstract: An organic light-emitting source includes a light-guiding substrate, at least one light-source area and a reflecting layer. The light-guiding substrate has a first surface and a second surface. The first surface includes at least one light-guiding part, which is a light guiding structure disposed on the light-guiding substrate. The light-source area includes at least one organic electroluminescent device, which sequentially includes a first electrode, at least one organic functional layer and a second electrode disposed over the first surface of the light-guiding substrate. The reflecting layer is disposed over the second surface of the light-guiding substrate.
    Type: Grant
    Filed: July 14, 2005
    Date of Patent: March 31, 2009
    Assignee: Ritdisplay Corporation
    Inventors: Yih Chang, Tien Rong Lu
  • Patent number: 7509444
    Abstract: This invention discloses a data access device for using in computer of power off status, which comprises a power multiplexer, a DC to DC converter, a serial bus signal to storage interface signal controller, a data storage interface signal multiplexer, and a controller. Therefore, if controller detects an external device wants to access data storage device of computer at power off, it will control power multiplexer to retrieve the standby power of the power device and process power transformation to provide a required power for driving the storage device, and by using serial bus signal to storage interface signal controller, external device can access the data from storage device at power off.
    Type: Grant
    Filed: September 14, 2005
    Date of Patent: March 24, 2009
    Assignee: Industrial Technology Research Institute
    Inventors: Chih-Yang Chiu, Ching-Chin Huang, Teng-Chieh Yang, Tsahn-Yih Chang, Yang-Chih Huang, Li-Hao Hsiao
  • Patent number: 7439597
    Abstract: An integrated circuit device for converting an incident optical signal into an electrical signal comprises a semiconductor substrate, a well region formed inside the semiconductor substrate, a dielectric layer formed over the well region, and a layer of polysilicon for receiving the incident optical signal, formed over the dielectric layer, including a p-type portion, an n-type portion and an undoped portion disposed between the p-type and n-type portions, wherein the well region is biased to control the layer of polysilicon for providing the electrical signal.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: October 21, 2008
    Inventors: Yu-Da Shiu, Chyh-Yih Chang, Ming-Dou Ker, Che-Hao Chuang
  • Patent number: 7435349
    Abstract: A system for treating wastewater containing organic compounds is provided, comprising an anaerobic bioreactor, an aerobic bioreactor disposed rearwardly of the anaerobic bioreactor, and a membrane separation reactor disposed rearwardly of the aerobic bioreactor. The system is capable of removing organic pollutants in wastewater through biological treatment process and separating solid from the liquid ones by using a membrane. By employing the system for treating wastewater containing organic pollutants, organic pollutants can be effectively eliminated and the problem of scaling and fouling on the surface of the membrane prevented, thus achieving the objectives of lowering cost and improving efficiency.
    Type: Grant
    Filed: March 14, 2006
    Date of Patent: October 14, 2008
    Assignee: Industrial Technology Research Institute
    Inventors: Huey-Song You, Ming-Jing Perage, Sheng-Shin Chang, Yih-Chang Chen, Shwu-Huey Perng
  • Publication number: 20070252615
    Abstract: A logic-keeping apparatus including a logic judgment unit and a noise-event detection unit is disclosed. When the level at the input terminal of the logic judgment unit is larger than a first level, the output terminal thereof outputs a first logic state; when the level at the input terminal is smaller than a second level, the output terminal thereof outputs a second logic state; when the level at the input terminal is between the first level and the second level, the output terminal thereof keeps the previous logic state. The noise-event detection unit is for detecting whether a noise-event occurs (for example, an ESD event). Wherein, when a noise-even occurs in the system, the noise-event detection unit keeps the level at the input terminal of the logic judgment unit between the first level and the second level.
    Type: Application
    Filed: June 23, 2006
    Publication date: November 1, 2007
    Inventors: Chyh-Yih Chang, Ching-Hua Huang
  • Patent number: 7288197
    Abstract: The present invention discloses a biological membrane filtration wastewater treatment system including a porous biological filtration bed zone and a membrane separation zone. The porous biological filtration bed zone has the dual function of providing biological treatment and higher filtration rates, wherein a fixed bed or moving bed is utilized so that the porous biological filtration bed zone has the advantages of high loading rates, high removal efficiencies, high stability and ease of operation. The membrane separation zone utilizes a membrane filtration module to filter an effluent from the porous biological filtration bed zone, so that solid particles therein are separated and remain in the system. Therefore, a high quality of effluent is obtained.
    Type: Grant
    Filed: April 4, 2005
    Date of Patent: October 30, 2007
    Assignee: Industrial Technology Research Institute
    Inventors: Hsin Shao, Wang-Kuan Chang, Ren-Yang Horng, Ming-Jing Perng, Ming-Chao Chang, Wen-Yuang Tzou, Yih-Chang Chen
  • Publication number: 20070247183
    Abstract: A logic-latching apparatus includes a noise-event detection unit, a combinational logic unit and a latch unit. The noise-event detection unit is used for detecting whether or not a noise-event occurs (for example, an ESD). The latch unit is coupled with the noise-event detection unit and the combinational logic unit for latching the state of the combinational logic unit. When the output of the noise-event detection unit indicates that a noise-event occurs, the latch unit provides the input terminal of the combinational logic unit with a corresponding input signal according to the latched state of the combinational logic unit inside the latch unit to prevent the state of the combinational logic unit from being affected by the noise-event.
    Type: Application
    Filed: May 11, 2006
    Publication date: October 25, 2007
    Inventors: Chyh-Yih Chang, Ching-Hua Huang
  • Publication number: 20070242054
    Abstract: A light transmission touch panel comprises a transparent substrate, a first transparent conductive layer, an insulation layer and a second transparent conductive layer, wherein the first transparent conductive layer, the insulation layer and the second transparent conductive layer are patterned and overlaid on a surface of the substrate. The first transparent conductive layer and the second transparent conductive layer are either on a surface or respectively on two opposite surfaces of the insulation layer. An electrical field having a component along the surface of the substrate occurs between two adjacent portions of the first transparent conductive layer and the second transparent conductive layer once they are electrically charged. When an article touches the touch panel, the intensity of the electrical lines is accordingly changed so that the touch panel can detect where the touch position is.
    Type: Application
    Filed: April 12, 2007
    Publication date: October 18, 2007
    Applicant: RITDISPLAY CORPORATION
    Inventors: Yih Chang, Tung-Yang Tang, Yuang-Wei Lai, Chun-Chieh Kuo, Ching-Lung Chen
  • Publication number: 20070240914
    Abstract: A transparent touch panel according to this aspect of the present invention comprises a transparent substrate, a capacitive touch device positioned on the transparent substrate, an interfacial structure positioned on the capacitive touch device, and a display device positioned on the interfacial structure. The capacitive touch device includes a plurality of first sensing blocks positioned on the transparent substrate, a dielectric layer covering the first sensing blocks, a plurality of second sensing blocks positioned on the dielectric layer, a plurality of first wires positioned on the transparent substrate, and a plurality of second wires positioned on the dielectric layer. Preferably, the first sensing blocks and the second sensing blocks are interlaced, each first wire connects the first sensing blocks on the same column, and each second wire connects the second sensing blocks on the same row.
    Type: Application
    Filed: April 12, 2007
    Publication date: October 18, 2007
    Applicant: RITDISPLAY CORPORATION
    Inventors: Yuang Wei Lai, Yih Chang, Tung Yang Tang, Chun Chieh Kuo
  • Publication number: 20070235808
    Abstract: An integrated circuit device that includes a semiconductor substrate, a well region formed inside the semiconductor substrate, a first isolation structure formed inside the well region, a second isolation structure formed inside the well region and spaced apart from the first isolation structure, a dielectric layer formed over the well region, and a layer of silicon, formed over the dielectric layer, including a p-type portion, an n-type portion and a center portion disposed between the p-type and n-type portions.
    Type: Application
    Filed: January 25, 2007
    Publication date: October 11, 2007
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chyh-Yih Chang, Ming-dou Ker
  • Publication number: 20070215991
    Abstract: A tape with a chip-bonding area is provided. The tape is suitable for a chip on film configuration, wherein a chip is suitable for being disposed on the tape and in the chip-bonding area. The tape includes a dielectric base film, a first wiring pattern, and at least a second wiring pattern. The first wiring pattern is disposed on the dielectric base film and has multiple inner leads disposed in the chip-bonding area. The second wiring pattern is disposed on the dielectric base film and in the chip-bonding area. The chip is suitable for being electrically connected to at least a part of the inner leads and being disposed above the second wiring pattern.
    Type: Application
    Filed: May 17, 2006
    Publication date: September 20, 2007
    Inventors: Chyh-Yih Chang, Kun-Hsien Tsai
  • Publication number: 20070210384
    Abstract: An integrated circuit device is disclosed that includes a semiconductor substrate, a well region formed inside the semiconductor substrate, and a first isolation structure formed inside the well region. Further, a second isolation structure is formed inside the well region and spaced apart from the first isolation structure, a dielectric layer is formed over the well region, and a layer of silicon, formed over the dielectric layer, including a p-type portion, an n-type portion, and a center portion is disposed between the p-type and n-type portions.
    Type: Application
    Filed: May 4, 2007
    Publication date: September 13, 2007
    Inventors: Chyh-Yih Chang, Ming-Dou Ker
  • Publication number: 20070200968
    Abstract: A display panel structure for improving electrostatic discharge (ESD) immunity is provided. The structure includes a first substrate, a pixel-array area, and an ESD protection path. The pixel-array area is disposed on the first substrate. At least one pixel unit and at least one data channel are disposed in the pixel-array area. The ESD protection path surrounds the pixel-array area to conduct an electrostatic current.
    Type: Application
    Filed: April 17, 2006
    Publication date: August 30, 2007
    Inventor: Chyh-Yih Chang
  • Publication number: 20070138589
    Abstract: An integrated circuit device for converting an incident optical signal into an electrical signal comprises a semiconductor substrate, a well region formed inside the semiconductor substrate, a dielectric layer formed over the well region, and a layer of polysilicon for receiving the incident optical signal, formed over the dielectric layer, including a p-type portion, an n-type portion and an undoped portion disposed between the p-type and n-type portions, wherein the well region is biased to control the layer of polysilicon for providing the electrical signal.
    Type: Application
    Filed: December 29, 2006
    Publication date: June 21, 2007
    Inventors: Yu-Da Shiu, Chyh-Yih Chang, Ming-Dou Ker, Che-Hao Chuang
  • Patent number: 7233468
    Abstract: A level shifter ESD protection circuit with power-on-sequence consideration used for receiving a first signal and outputting a second signal is provided. The level shifter circuit includes an inverter, a first switch, a second switch, a voltage level shifting circuit, a first ESD clamp and a second ESD clamp circuits. When the first power supply has been powered on and the second power supply is off, the first and second switches will remain off resulting from the power-off of the second power supply. Therefore, the second power source would not be affected by the first power supply because of passing through the ESD protection circuit.
    Type: Grant
    Filed: September 19, 2005
    Date of Patent: June 19, 2007
    Assignee: Novatek Microelectronics Corp.
    Inventors: Chyh-Yih Chang, Kuo-Ching Chen
  • Publication number: 20070126073
    Abstract: An integrated circuit device for converting an incident optical signal into an electrical signal comprises a semiconductor substrate, a well region formed inside the semiconductor substrate, a dielectric layer formed over the well region, and a layer of polysilicon for receiving the incident optical signal, formed over the dielectric layer, including a p-type portion, an n-type portion and an undoped portion disposed between the p-type and n-type portions, wherein the well region is biased to control the layer of polysilicon for providing the electrical signal.
    Type: Application
    Filed: December 29, 2006
    Publication date: June 7, 2007
    Inventors: Yu-Da Shiu, Chyh-Yih Chang, Ming-Dou Ker, Che-Hao Chuang