Abstract: A bi-directional buffer includes first and second unidirectional buffers connected for retransmitting signals in opposite directions between first and second buses. When an external bus driver pulls the first bus low, the first unidirectional buffer pulls the second bus low and generates a signal inhibiting the second unidirectional buffer from actively driving the first bus. When the external bus driver allows the first bus to return to the high logic level, the first unidirectional buffer temporarily supplies a high charging current to the second bus to quickly pull it up. Similarly, when an external bus driver pulls the second bus low, the second unidirectional buffer pulls the first bus low and generates a signal inhibiting the first unidirectional buffer from actively driving the second bus. When the external bus driver allows the second bus to return to the high logic level, the second buffer temporarily supplies a high charging current to the first bus to quickly pull it up.

Abstract: A field programmable circuit board provides a set of sockets for receiving electronic components, a set of connector pins for providing external access to the board and an array of field programmable interconnect devices (FPIDs). The FPIDs are buffered, multiple port cross-point switches that may be programmed by a host computer to selectively connect terminals of the components mounted in the sockets to one another or to the external connector pins. Signal buffers within the FPID ports automatically sense direction of flow of bidirectional signals routed by the FPIDs and buffer the signals in the appropriate direction. Each FPID buffer also samples and stores data indicating states of the buffered signals over several system clock cycles for subsequent read out by the host computer.

Abstract: A bi-directional bus repeater includes two unidirectional bus repeaters connected for retransmitting signals in opposite directions between two buses. When an external bus driver pulls either bus low, one of the unidirectional bus repeaters pulls the other bus low. When the external bus driver allows the bus to rise to the high logic level, the unidirectional bus repeater temporarily supplies a high charging current to the other bus to quickly pull it up. Each unidirectional bus repeater also generates signals indicating when it is actively pulling its output bus up or down and the indicating signals inhibit one unidirectional bus repeater from actively driving its output when the other unidirectional bus repeater is actively driving its output.

Abstract: A system for testing electronic devices includes a waveform generator, a data acquisition system, and a computer. The waveform generator continuously generates a test signal having adjustable parameters set by the computer in response to user input. The data acquisition system acquires data representing the output of the device under test in response to the input signal and stores the last N acquired data values. The computer transfers a data sequence from the acquisition system to another memory and generates in a window on a terminal screen a wagveform display representing the stored data sequence. The computer also displays menu items referencing mathematical operations that may be performed on one or more data sequences. When a user selects one of the menu items, the computer prompts the user to select one or more windows containing waveform displays. Thereafter, the computer performs the selected operation on the data sequence controlling the waveform displays in the selected windows.

Abstract: Jitter in a clock signal is measured by using the clock signal to clock a digitizer repetitively digitizing a highly stable sine wave signal so as to produce a first data sequence representing the magnitiude of the sine wave signal as a function of time. This first data sequence is normalized to produce a second data sequence having data elements that vary between maximum and minimun magnitudes of +1 and -1. The arcsine of each element of the second data sequence is then determined to provide a monotonically increasing third data sequence, wherein each element of the third data sequence indicates a phase angle associated with a corresponding element of the second data sequence. A fourth data sequence is then generated, each element of the fourth data sequence representing a difference between a phase angle represented by a corresponding element of the third data sequence and a phase angle that the corresponding element of the third data sequence would represent if the clock signal had a constant frequency.

Abstract: A method and apparatus for determining the effective bits of resolution of a digitizer wherein amplitude, frequency, phase angle and offset parameters characterizing a sinewave input signal to the digitizer are estimated from the waveform data sequence produced by the digitizer in response to the input signal. These estimated parameters are used to develop a model of the sinewave signal, and the effective bits of resolution of the digitizer are then determined by the comparing measured magnitudes of the sinewave signal as represented by the waveform data sequence to estimated magnitudes of the input signal being determined from the model.

Abstract: Stored waveform records representative of respective repetitions of a repetitive signal are processed by reading a first waveform record from memory to form a reference signal. A second waveform record is read from memory to form a second signal, and the second signal is shifted in time in such a manner as to minimize the power of a difference signal, of which the instantaneous magnitude is representative of the difference in instantaneous magnitude between the reference signal and the time-shifted second signal. If the waveform records are identical but for jitter, and the power of the difference signal is brought to zero, this implies that the first waveform signal is synchronous with the processed second waveform signal, i.e., there is no jitter between the two signals.

Abstract: A two-dimensional array of binary values is used to control operation of a bi-level imaging device. The array of binary values is formed by applying an enhanced array g(u,v) to a two-dimensional array of threshold values. A two-dimensional array of pixel value f(u,v) is used to form the enhanced array g(u,v) such that g(u,v)=m.sub.f +k[f(u,v)-m.sub.f ] where m.sub.f is the average value of f(u+a, v+b) from a=-L to a=+L and b=-M to b=+M and k is a gain function which depends on the standard deviation in f(u+c, v+d) from c=-N to c=+N and d=-P to d=+P. L, M, N and P define the sub-array over which the standard deviation is calculated. Preferably, L, M, N and P are each equal to 2. The value of k is a decreasing function of the standard deviation: the larger the standard deviation, the smaller the gain factor k. The rate at which k decreases with increase in the standard deviation depends on the edge sampling characteristics of the array of threshold values.

Abstract: A digital pipelined heterodyne circuit includes sine and cosine function generators for generating m-bit digital coefficients and an m-stage digital multiplier for multiplying the coefficients by a digitized data input signal. A triangular shift register array connects the digital sine and cosine function generators with the multiplier stages and provides for simultaneous processing of successive bytes of input data at each multiplier stage by delaying the arrival of coefficient bits at each multiplier stage to coincide with the arrival of a predetermined data byte. This takes place simultaneously in all stages thereby decreasing the processing time by a factor of m.

Abstract: A digitizer system includes M digitizers, each producing a separate waveform data sequence representing a succession of instantaneous magnitudes of an input signal at sample times determined by a periodic clock signal. Transmission of the clock signal to each digitizer is delayed by a corresponding adjustable delay time so as to control the relative sample timing of the digitizers. To adjust sample timing, a sine wave signal is applied as the input signal to each digitizer such that the M digitizers produce M separate waveform data sequences in response to said input signal and the M data sequences are interleaved and windowed to form a single waveform data sequence. A first sequence of complex numbers representing a discrete Fourier transform of the single waveform data sequence is generated and then a second sequence of M complex numbers is formed from elements corresponding to relative magnitude peaks of the first sequence.