Patents by Inventor Yih-Hsiung Lin

Yih-Hsiung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Surface treatment of metal interconnect lines
    Patent number: 8053894
    Abstract: Apparatus for forming a semiconductor structure comprising a first layer on top of a substrate wherein the first layer defines conductive regions such as copper interconnect lines and non-conductive regions such as dielectric materials. The conductive regions are covered by a second layer of a material different than the first layer such as for example nickel and then the structure is heat treated such that the interconnect lines and second metal, such as a copper interconnect line and a nickel second layer, interact with each other to form an alloy layer. The alloy layer has superior qualities for adhering to both the copper interconnect lines and a subsequently deposited dielectric material.
    Type: Grant
    Filed: August 26, 2005
    Date of Patent: November 8, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Kai Wan, Yih-Hsiung Lin, Ming-Ta Lei, Baw-Ching Perng, Cheng-Chung Lin, Chia-Hui Lin, Ai-Sen Liu
  • Integration film scheme for copper / low-k interconnect
    Patent number: 7244673
    Abstract: A structure for a multi-level interconnect inter-level dielectric layer (ILD), a method of manufacturing thereof, and a semiconductor device including the ILD layer. The ILD layer includes a first low-dielectric constant material sub-layer, and a second low-dielectric constant material sub-layer disposed over the first low-dielectric constant material sub-layer. The second low-dielectric constant material sub-layer has at least one different material property than the first low-dielectric constant material sub-layer. A third low-dielectric constant material sub-layer is disposed over the second low-dielectric constant material sub-layer, the third low-dielectric constant material sub-layer having at least one different material property than the second low-dielectric constant material sub-layer.
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: July 17, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tai-Chun Huang, Chih-Hsiang Yao, Yih-Hsiung Lin, Tien-I Bao, Bi-Trong Chen, Yung-Cheng Lu
  • Surface treatment of metal interconnect lines
    Publication number: 20060001160
    Abstract: Apparatus for forming a semiconductor structure comprising a first layer on top of a substrate wherein the first layer defines conductive regions such as copper interconnect lines and non-conductive regions such as dielectric materials. The conductive regions are covered by a second layer of a material different than the first layer such as for example nickel and then the structure is heat treated such that the interconnect lines and second metal, such as a copper interconnect line and a nickel second layer, interact with each other to form an alloy layer. The alloy layer has superior qualities for adhering to both the copper interconnect lines and a subsequently deposited dielectric material.
    Type: Application
    Filed: August 26, 2005
    Publication date: January 5, 2006
    Inventors: Wen-Kai Wan, Yih-Hsiung Lin, Ming-Ta Lei, Baw-Ching Perng, Cheng-Chung Lin, Chia-Hui Lin, Ai-Sen Liu
  • Surface treatment of metal interconnect lines
    Patent number: 6955984
    Abstract: Methods and apparatus for forming a semiconductor structure comprising a first layer on top of a substrate wherein the first layer defines conductive regions such as copper interconnect lines and non-conductive regions such as dielectric materials. The conductive regions are covered by a second layer of a material different than the first layer such as for example nickel and then the structure is heat treated such that the interconnect lines and second metal, such as a copper interconnect line and a nickel second layer, interact with each other to form an alloy layer. The alloy layer has superior qualities for adhering to both the copper interconnect lines and a subsequently deposited dielectric material.
    Type: Grant
    Filed: May 16, 2003
    Date of Patent: October 18, 2005
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Kai Wan, Yih-Hsiung Lin, Ming-Dai Lei, Baw-Ching Perng, Cheng-Chung Lin, Chia-Hui Lin, Ai-Sen Liu
  • Integration film scheme for copper / low-k interconnect
    Publication number: 20050098896
    Abstract: A structure for a multi-level interconnect inter-level dielectric layer (ILD), a method of manufacturing thereof, and a semiconductor device including the ILD layer. The ILD layer includes a first low-dielectric constant material sub-layer, and a second low-dielectric constant material sub-layer disposed over the first low-dielectric constant material sub-layer. The second low-dielectric constant material sub-layer has at least one different material property than the first low-dielectric constant material sub-layer. A third low-dielectric constant material sub-layer is disposed over the second low-dielectric constant material sub-layer, the third low-dielectric constant material sub-layer having at least one different material property than the second low-dielectric constant material sub-layer.
    Type: Application
    Filed: November 12, 2003
    Publication date: May 12, 2005
    Inventors: Tai-Chun Huang, Chih-Hsiang Yao, Yih-Hsiung Lin, Tien-I Bao, Bi-Trong Chen, Yung-Cheng Lu
  • Surface treatment of metal interconnect lines
    Publication number: 20040229460
    Abstract: Methods and apparatus for forming a semiconductor structure comprising a first layer on top of a substrate wherein the first layer defines conductive regions such as copper interconnect lines and non-conductive regions such as dielectric materials. The conductive regions are covered by a second layer of a material different than the first layer such as for example nickel and then the structure is heat treated such that the interconnect lines and second metal, such as a copper interconnect line and a nickel second layer, interact with each other to form an alloy layer. The alloy layer has superior qualities for adhering to both the copper interconnect lines and a subsequently deposited dielectric material.
    Type: Application
    Filed: May 16, 2003
    Publication date: November 18, 2004
    Inventors: Wen-Kai Wan, Yih-Hsiung Lin, Ming-Ta Lei, Baw-Ching Perng, Cheng-Chung Lin, Chia-Hui Lin, Ai-Sen Liu
  • Clock
    Patent number: D362393
    Type: Grant
    Filed: January 4, 1994
    Date of Patent: September 19, 1995
    Inventor: Yih-Hsiung Lin