Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.

Abstract: Provided are structures and methods for forming structures with sloping surfaces of a desired profile. An exemplary method includes performing a first etch process to differentially etch a gate material to a recessed surface, wherein the recessed surface includes a first horn at a first edge, a second horn at a second edge, and a valley located between the first horn and the second horn; depositing an etch-retarding layer over the recessed surface, wherein the etch-retarding layer has a central region over the valley and has edge regions over the horns, and wherein the central region of the etch-retarding layer is thicker than the edge regions of the etch-retarding layer; and performing a second etch process to recess the horns to establish the gate material with a desired profile.

Abstract: Disclosed is a semiconductor fabrication method. The method includes forming a gate stack in an area previously occupied by a dummy gate structure; forming a first metal cap layer over the gate stack; forming a first dielectric cap layer over the first metal cap layer; selectively removing a portion of the gate stack and the first metal cap layer while leaving a sidewall portion of the first metal cap layer that extends along a sidewall of the first dielectric cap layer; forming a second metal cap layer over the gate stack and the first metal cap layer wherein a sidewall portion of the second metal cap layer extends further along a sidewall of the first dielectric cap layer; forming a second dielectric cap layer over the second metal cap layer; and flattening a top layer of the first dielectric cap layer and the second dielectric cap layer using planarization operations.

Abstract: A process to select signature gene by performing statistical analyses on gene datasets of various types of diseases for identifying signature genes for at least one of the diseases followed by categorizing and establishing gene expression table with the signature genes. The signature genes in the gene expression table are tested and verified by applying additional datasets to finalize and confirm the signature genes. The step of performing the statistical analyses on the gene datasets of various types of diseases further comprising a step of performing a total background normalization (TBN) of a relative gene expression (RGE) ratio then carried a two-tail T-test of the RGE ratios between the various diseases.

Abstract: An exonuclease-based method for joining and/or constructing two or more DNA molecules. DNA fragments containing ends complementary to those of a vector or another independent molecule were generated by the polymerase chain reaction. The 3' ends of these molecules as well as the vector DNA were then recessed by exonuclease activity and annealed in an orientation-determined manner via their complementary single-stranded regions. This recombinant DNA may be transformed directly into bacteria without a further ligase-dependent reaction. Using this approach, recombinant DNA molecules are constructed rapidly, efficiently and directionally. This method can effectively replace conventional protocols for PCR cloning, PCR SOEing, DNA subcloning and site-directed mutagenesis.