Abstract: An embodiment of a memory controller device includes technology to control access to a memory array which includes a single-level cell region and a multi-level cell region, determine an amount of valid data in a dynamic portion of the single-level cell region at runtime, and adjust a size of the dynamic portion of the single-level cell region at runtime based on the determined amount of valid data in the dynamic portion of the single-level cell region. Other embodiments are disclosed and claimed.

Abstract: Direct data transfer between devices having a shared bus may be implemented with reduced involvement from a controller associated with the devices. A controller, a source memory device, and a target memory device may be coupled with a shared bus. The controller may identify a source address at the source memory device for data to be transferred to the target memory device. The controller also may identify a target address in the target memory device, and initiate a data transfer directly from the source to the target through a command that is received at both the source and the target memory device. In response to the command, the source memory device may read data out to the bus, and the target memory may read the data from the bus and store the data starting at the target address without further commands from the controller.

Abstract: A nonvolatile (NV) memory device includes an NV storage media and a storage controller to control access to the NV storage media. In response to a host read request, the storage controller can determine if the NV storage media is in a stable Vt (threshold voltage) state. If the NV storage media is in a stable Vt state, the storage controller can perform a reset read operation prior to servicing the host read request. A reset read is a read operation that does not produce data to send back to the host. The reset read operation is a dummy read that puts the NV storage media into a transient Vt state, which has lower risk of read disturb.

Abstract: Techniques for preventing read disturb in NAND memory devices are described. In one example, reads are tracked for sub-groups. When the number of reads to a sub-group meets a threshold, the data at the wordline on which the threshold was met is moved along with the data at neighboring wordlines to an SLC block without moving the entire block. The performance impact and write amplification impact of read disturb mitigation can be significantly reduced while maintaining some data continuity.

Abstract: A family of new crystalline molecular sieves designated SSZ-91 is disclosed, as are methods for making SSZ-91 and uses for SSZ-91. Molecular sieve SSZ-91 is structurally similar to sieves falling within the ZSM-48 family of molecular sieves, and is characterized as: (1) having a low degree of faulting, (2) a low aspect ratio that inhibits hydrocracking as compared to conventional ZSM-48 materials having an aspect ratio of greater than 8, and (3) is substantially phase pure.

Abstract: Methods, systems, and devices for operating a memory cell or cells are described. An error in stored data may be detected by an error correction code (ECC) operation during sensing of the memory cells used to store the data. The error may be indicated in hardware by generating a measurable signal on an output node. For example, the voltage at the output node may be changed from a first value to a second value. A device monitoring the output node may determine an error has occurred for a set of data based at least in part on the change in the signal at the output node.

Abstract: Subject matter disclosed herein relates to techniques to read memory in a continuous fashion.

Abstract: Methods, systems, and devices for operating a memory cell or cells are described. An error in stored data may be detected by an error correction code (ECC) operation during sensing of the memory cells used to store the data. The error may be indicated in hardware by generating a measurable signal on an output node. For example, the voltage at the output node may be changed from a first value to a second value. A device monitoring the output node may determine an error has occurred for a set of data based at least in part on the change in the signal at the output node.

Abstract: Write performance of a block-based multi-level cell non-volatile memory is increased through the use of an internal copy of blocks with a high validity. Write (program) performance for sequential workloads is increased by moving the data in blocks with a high validity within a NAND device directly from the portion of the NAND device configured as single level cell NAND to the portion of the NAND device configured as multi-level cell NAND.

Abstract: Subject matter disclosed herein relates to techniques to read memory in a continuous fashion.

Abstract: Direct data transfer between devices having a shared bus may be implemented with reduced involvement from a controller associated with the devices. A controller, a source memory device, and a target memory device may be coupled with a shared bus. The controller may identify a source address at the source memory device for data to be transferred to the target memory device. The controller also may identify a target address in the target memory device, and initiate a data transfer directly from the source to the target through a command that is received at both the source and the target memory device. In response to the command, the source memory device may read data out to the bus, and the target memory may read the data from the bus and store the data starting at the target address without further commands from the controller.

Abstract: A new crystalline molecular sieve designated SSZ-95 is disclosed. In general, SSZ-95 is synthesized from a reaction mixture suitable for synthesizing MTT-type molecular sieves and maintaining the mixture under crystallization conditions sufficient to form product. The product molecular sieve is subjected to a pre-calcination step, and ion-exchange to remove extra-framework cations, and a post-calcination step. The molecular sieve has a MTT-type framework and a H-D exchangeable acid site density of 0 to 50% relative to molecular sieve SSZ-32.

Abstract: A second-stage hydrocracking catalyst is provided, comprising: a) a zeolite beta having an OD acidity of 20 to 400 ?mol/g and an average domain size from 800 to 1500 nm2; b) a zeolite USY having an ASDI between 0.05 and 0.12; c) a catalyst support; and d) 0.1 to 10 wt % noble metal; wherein the second-stage hydrocracking catalyst provides a hydrogen consumption less than 350 SCFB across a range of synthetic conversions up to 37 wt % when used to hydrocrack hydrocarbonaceous feeds having an initial boiling point greater than 380° F. (193° C.). A second-stage hydrocracking process using the second-stage hydrocracking process is provided. A method to make the second-stage hydrocracking catalyst is also provided.

Abstract: A hydrocracking catalyst is provided comprising: a) greater than 10 wt % of a zeolite USY having: i. a total OD acidity of 0.350 to 0.650 mmol/g; ii. an ASDI between 0.05 and 0.15; iii. a BET surface area greater than 600 m2/g; iv. a SAR greater than 10; v. less than 45 vol % of pores greater than 2 nm; b) a support; and c) at least one metal selected from the group consisting of elements from Group 6 and Groups 8 through 10 of the Periodic Table. A process for hydrocracking using a hydrocracking catalyst to produce middle distillates is provided. A method for making a hydrocracking catalyst is also provided.

Abstract: A second-stage hydrocracking catalyst is provided comprising: a. from 40 wt % to 70 wt % of a zeolite USY having an ASDI from 0.05 to 0.18; b. an amorphous silica alumina; c. a second alumina; and d. 0.1 to 10 wt % noble metal; wherein the second-stage hydrocracking catalyst has a BET surface area from 450 to 650 m2/g. A second-stage hydrocracking process is provided comprising using the second-stage hydrocracking catalyst to produce middle distillate. A method for making the second-stage hydrocracking catalyst is also provided.

Abstract: A second-stage hydrocracking catalyst is provided, comprising: a) a zeolite beta having an OD acidity of 20 to 400 ?mol/g and an average domain size from 800 to 1500 nm2; b) a zeolite USY having an ASDI between 0.05 and 0.12; c) a catalyst support; and d) 0.1 to 10 wt % noble metal; wherein the second-stage hydrocracking catalyst provides a hydrogen consumption less than 350 SCFB across a range of synthetic conversions up to 37 wt % when used to hydrocrack hydrocarbonaceous feeds having an initial boiling point greater than 380° F. (193° C.). A second-stage hydrocracking process using the second-stage hydrocracking process is provided. A method to make the second-stage hydrocracking catalyst is also provided.

Abstract: A method of data transmission includes: receiving a first packet, where the first packet includes first compressed data and a first check value, the first compressed data is obtained by compressing first data based on a first compression mode, the first check value is obtained by processing a second check value based on a first check algorithm, the second check value is obtained by processing the first compressed data based on a second check algorithm; obtaining a first check code by processing the first packet based on a third check algorithm; determining, according to a correspondence between the first check code and the first compression mode, that the first compression mode is a compression mode used when the first data is compressed; and obtaining the first data by decompressing, based on a first decompression mode corresponding to the first compression mode, the first compressed data included in the first packet.

Abstract: A family of new crystalline molecular sieves designated SSZ-91 is disclosed, as are methods for making SSZ-91 and uses for SSZ-91. Molecular sieve SSZ-91 is structurally similar to sieves falling within the ZSM-48 family of molecular sieves, and is characterized as: (1) having a low degree of faulting, (2) a low aspect ratio that inhibits hydrocracking as compared to conventional ZSM-48 materials having an aspect ratio of greater than 8, and (3) is substantially phase pure.

Abstract: A new crystalline molecular sieve designated SSZ-95 is disclosed. In general, SSZ-95 is synthesized from a reaction mixture suitable for synthesizing MTT-type molecular sieves and maintaining the mixture under crystallization conditions sufficient to form product. The product molecular sieve is subjected to a pre-calcination step, and ion-exchange to remove extra-framework cations, and a post-calcination step. The molecular sieve has a MTT-type framework and a H-D exchangeable acid site density of 0 to 50% relative to molecular sieve SSZ-32.

Abstract: Direct data transfer between devices having a shared bus may be implemented with reduced involvement from a controller associated with the devices. A controller, a source memory device, and a target memory device may be coupled with a shared bus. The controller may identify a source address at the source memory device for data to be transferred to the target memory device. The controller also may identify a target address in the target memory device, and initiate a data transfer directly from the source to the target through a command that is received at both the source and the target memory device. In response to the command, the source memory device may read data out to the bus, and the target memory may read the data from the bus and store the data starting at the target address without further commands from the controller.