Abstract: Disclosed are systems and methods for superimposing a virtual image on a real-time image. A system for superimposing a virtual image on a real-time image comprises a real-time image module and a virtual image module. The real-time image module comprises a magnification assembly to generate a real-time image of an object at a first location and a first depth, with a predetermined magnification. The virtual image module generates a virtual image by respectively projecting a right light signal to a viewer's right eye and a corresponding left light signal to a viewer's left eye. The right light signal and the corresponding left light signal are perceived by the viewer to display the virtual image at a second location and a second depth. The second depth is related to an angle between the right light signal and the corresponding left light signal projected to the viewer's eyes. The second depth may be approximately the same as the first depth.

Abstract: The present invention is related to a novel positive electrode active material for lithium-ion battery. The positive electrode active material is expressed by the following formula: Li1.2NixMn0.8-x-yZnyO2, wherein x and y satisfy 0<x?0.8 and 0<y?0.1. In addition, the present invention provides a method of manufacturing the positive electrode active material. The present invention further provides a lithium-ion battery which uses said positive electrode active material.

Abstract: A memory circuit includes a memory unit, a memory control circuit and a pseudo ground voltage generation circuit. The memory control circuit includes: a level shifter circuit coupled to a variable supply voltage; a driver circuit coupled to the pseudo ground voltage generation circuit at the pseudo ground node. The driver circuit is powered by the variable supply voltage and generates an access signal according to the driving signal, to access data from the memory unit. Under a high-voltage operation, the variable supply voltage provides a first supply voltage level, so that a high level of the access signal corresponds to the first supply voltage level and the pseudo ground voltage generation circuit provides a pseudo ground voltage level at the pseudo ground node. A voltage difference between the first supply voltage level and the pseudo ground voltage level is smaller than a withstand voltage of the driver circuit.

Abstract: A memory circuit includes a memory unit, a memory control circuit and a pseudo ground voltage generation circuit. The memory control circuit includes: a level shifter circuit coupled to a variable supply voltage; a driver circuit coupled to the pseudo ground voltage generation circuit at the pseudo ground node. The driver circuit is powered by the variable supply voltage and generates an access signal according to the driving signal, to access data from the memory unit. Under a high-voltage operation, the variable supply voltage provides a first supply voltage level, so that a high level of the access signal corresponds to the first supply voltage level and the pseudo ground voltage generation circuit provides a pseudo ground voltage level at the pseudo ground node. A voltage difference between the first supply voltage level and the pseudo ground voltage level is smaller than a withstand voltage of the driver circuit.

Abstract: A sense amplifier for a memory includes a transistor, an operational amplifier, and a compensating circuit. The negative input end of the operational amplifier is coupled to the compensating circuit. The positive input end of the operational amplifier is coupled to the drain of the transistor. The output end of the operational amplifier is coupled to the gate of the transistor. The compensating circuit is coupled between the negative input end and the output end of the operational amplifier. The compensating circuit generates a compensating voltage to the negative input end of the operational amplifier according to the voltage of the gate of the transistor.

Abstract: A control driver for non-volatile memory includes a driving circuit, a level shift up circuit, and a select circuit. The select circuit receives a plurality of decoding signals, asserts a select signal when all of the decoding signals are asserted, and does not assert the select signal when any of the decoding signals is not asserted. The level shift up circuit receives the select signal, outputs the pull-up signal at a first voltage when the select signal is asserted, and outputs the pull-up signal at a second voltage when the select signal is not asserted. The driving circuit has a pull-up transistor for pulling up a control line signal according to the pull-up signal, and a pull-down transistor for pulling down the control line signal according to the pull-up signal.

Abstract: A control driver for non-volatile memory includes a driving circuit, a level shift up circuit, and a select circuit. The select circuit receives a plurality of decoding signals, asserts a select signal when all of the decoding signals are asserted, and does not assert the select signal when any of the decoding signals is not asserted. The level shift up circuit receives the select signal, outputs the pull-up signal at a first voltage when the select signal is asserted, and outputs the pull-up signal at a second voltage when the select signal is not asserted. The driving circuit has a pull-up transistor for pulling up a control line signal according to the pull-up signal, and a pull-down transistor for pulling down the control line signal according to the pull-up signal.

Abstract: A sense amplifier for a memory includes a transistor, an operational amplifier, and a compensating circuit. The negative input end of the operational amplifier is coupled to the compensating circuit. The positive input end of the operational amplifier is coupled to the drain of the transistor. The output end of the operational amplifier is coupled to the gate of the transistor. The compensating circuit is coupled between the negative input end and the output end of the operational amplifier. The compensating circuit generates a compensating voltage to the negative input end of the operational amplifier according to the voltage of the gate of the transistor.

Abstract: A two-phase charge pump circuit without the body effect includes a voltage boost stage, an input stage connected to the voltage boost stage, and a high-voltage generator connected to the input stage. Each of the circuits can consist of NMOS or PMOS transistors. The body of each NMOS transistor is connected to an NMOS switch. The body of each PMOS transistor is connected to a PMOS switch. By providing an appropriate driving signal to each NMOS or PMOS switch, the body of each NMOS transistor can be switched to a lower voltage level and the body of each PMOS transistor is switched to a higher voltage level. This can prevent the body effect from occurring.

Abstract: A memory apparatus includes a plurality of memory units, a sensing circuit and a bias-generating circuit. The plurality of memory units respectively outputs a data current to the sensing circuit, while the sensing circuit further includes a plurality of first transistors, a plurality of second transistors and a plurality of sensing amplifiers. In order to speed up the access time of the memory units, the bias-generating circuit rapidly provides a bias signal to the sensing circuit to turn on the first transistors of the sensing circuit. In the present invention, the sensing circuit uses a common reference voltage to reduce the circuit utilization area of the memory apparatus.

Abstract: Non-volatile memory includes a row driving circuit with shared level shift circuits, so as to minimize the chip area of the non-volatile memory. The row driving circuit includes a plurality of word line driving circuits, a plurality of level shift high circuits, and a plurality of level shift low circuits. The plurality of word line driving circuits share the plurality of level shift high circuits and the plurality of level shift low circuits. Each word line driving circuit includes a plurality of driving units, a level shift high circuit, and a level shift low circuit. The plurality of driving units share the level shift high circuit and the level shift low circuit of the word line driving circuit.

Abstract: A two-phase charge pump circuit without the body effect includes a voltage boost stage, an input stage connected to the voltage boost stage, and a high-voltage generator connected to the input stage. Each of the circuits can consist of NMOS or PMOS transistors. The body of each NMOS transistor is connected to an NMOS switch. The body of each PMOS transistor is connected to a PMOS switch. By providing an appropriate driving signal to each NMOS or PMOS switch, the body of each NMOS transistor can be switched to a lower voltage level and the body of each PMOS transistor is switched to a higher voltage level. This can prevent the body effect from occurring.

Abstract: A memory apparatus includes a plurality of memory units, a sensing circuit and a bias-generating circuit. The plurality of memory units respectively outputs a data current to the sensing circuit, while the sensing circuit further includes a plurality of first transistors, a plurality of second transistors and a plurality of sensing amplifiers. In order to speed up the access time of the memory units, the bias-generating circuit rapidly provides a bias signal to the sensing circuit to turn on the first transistors of the sensing circuit. In the present invention, the sensing circuit uses a common reference voltage to reduce the circuit utilization area of the memory apparatus.

Abstract: A two-phase charge pump circuit without the body effect includes a voltage boost stage, an input stage connected to the voltage boost stage, and a high-voltage generator connected to the input stage. Each of the circuits can consist of NMOS or PMOS transistors. The body of each NMOS transistor is connected to an NMOS switch. The body of each PMOS transistor is connected to a PMOS switch. By providing an appropriate driving signal to each NMOS or PMOS switch, the body of each NMOS transistor can be switched to a lower voltage level and the body of each PMOS transistor is switched to a higher voltage level. This can prevent the body effect from occurring.

Abstract: Non-volatile memory includes a row driving circuit with shared level shift circuits, so as to minimize the chip area of the non-volatile memory. The row driving circuit includes a plurality of word line driving circuits, a plurality of level shift high circuits, and a plurality of level shift low circuits. The plurality of word line driving circuits share the plurality of level shift high circuits and the plurality of level shift low circuits. Each word line driving circuit includes a plurality of driving units, a level shift high circuit, and a level shift low circuit. The plurality of driving units share the level shift high circuit and the level shift low circuit of the word line driving circuit.

Abstract: A regulator circuit having a voltage output terminal is provided. The regulator circuit includes a current mirror module, a plurality of source followers, and a switch. The current module receives a driving voltage, and has a first current terminal coupled to a driving current and a plurality of second current terminals, so that the driving current is copied to each second current terminal. Furthermore, each of second current terminals is coupled to one of source followers respectively. An output terminal of each source follower is coupled to an input terminal of next source, and the input terminal of the first source follower receives a control voltage. So that the source followers can determine whether the switch conducts the driving voltage to the voltage output terminal or not according to the copied driving current and the control voltage.

Abstract: The voltage source and current source circuits including an amplifier, a first current mirror circuit, a first PMOS transistor, a second current mirror circuit and a NMOS transistor are provided. The amplifier has a positive input terminal and a negative input terminal coupled to the source terminal of the NMOS transistor. The first current mirror circuit is coupled to a reference current and duplicates the reference current to the source terminal of the first PMOS transistor. The first PMOS transistor has a drain terminal, a gate terminal and a source terminal. The drain terminal of the NMOS transistor is coupled to the third current terminal, and the gate terminal of the NMOS transistor is coupled to the source terminal of the first PMOS transistor. The second current mirror circuit duplicates the current from the third current terminal.

Abstract: The voltage source and current source circuits including an amplifier, a first current mirror circuit, a first PMOS transistor, a second current mirror circuit and a NMOS transistor are provided. The amplifier has a positive input terminal and a negative input terminal coupled to the source terminal of the NMOS transistor. The first current mirror circuit is coupled to a reference current and duplicates the reference current to the source terminal of the first PMOS transistor. The first PMOS transistor has a drain terminal, a gate terminal and a source terminal. The drain terminal of the NMOS transistor is coupled to the third current terminal, and the gate terminal of the NMOS transistor is coupled to the source terminal of the first PMOS transistor. The second current mirror circuit duplicates the current from the third current terminal.

Abstract: A regulator circuit having a voltage output terminal is provided. The regulator circuit includes a current mirror module, a plurality of source followers, and a switch. The current module receives a driving voltage, and has a first current terminal coupled to a driving current and a plurality of second current terminals, so that the driving current is copied to each second current terminal. Furthermore, each of second current terminals is coupled to one of source followers respectively. An output terminal of each source follower is coupled to an input terminal of next source, and the input terminal of the first source follower receives a control voltage. So that the source followers can determine whether the switch conducts the driving voltage to the voltage output terminal or not according to the copied driving current and the control voltage.

Abstract: A boost circuit capable of boosting a reference voltage into an output voltage. The boost circuit includes a main transistor electrically connected to the output voltage, an auxiliary transistor electrically connected to the output voltage, a pre-charge circuit electrically connected to the main transistor and the auxiliary transistor for pre-charging the main transistor and the auxiliary transistor, and a voltage detector electrically connected to the auxiliary transistor and the reference voltage for controlling the auxiliary transistor according to the reference voltage.