Patents by Inventor Yin FAN
Yin FAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240118349Abstract: The disclosure discloses a battery device, a detection method thereof, a method and device for screening battery cells. The characteristic values are determined according to parameters of two peaks in the frequency-domain impedance diagram. The characteristic values may reflect the magnitude of charge transfer impedance and diffusion impedance in each battery cell, then reflect the characteristics of the interface and characteristics of solid phase particles during charging and discharging, and further reflect the health and performance of battery cells. The battery set screened in this way still have good consistency after storage and shelving, and the consistency between battery cells will not deteriorate after storage for a period of time, so that the battery device may have better performance.Type: ApplicationFiled: December 1, 2022Publication date: April 11, 2024Applicant: CALB Co., Ltd.Inventors: Ruijun Ma, Fengsong Fan, Shengjie Wang, Yin Liu, Kui Li
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Publication number: 20240099154Abstract: A magnetoresistive random access memory (MRAM) device includes a first array region and a second array region on a substrate, a first magnetic tunneling junction (MTJ) on the first array region, a first top electrode on the first MTJ, a second MTJ on the second array region, and a second top electrode on the second MTJ. Preferably, the first top electrode and the second top electrode include different nitrogen to titanium (N/Ti) ratios.Type: ApplicationFiled: November 21, 2023Publication date: March 21, 2024Applicant: UNITED MICROELECTRONICS CORPInventors: Hui-Lin Wang, Si-Han Tsai, Dong-Ming Wu, Chen-Yi Weng, Ching-Hua Hsu, Ju-Chun Fan, Yi-Yu Lin, Che-Wei Chang, Po-Kai Hsu, Jing-Yin Jhang
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Patent number: 11917923Abstract: A magnetoresistive random access memory (MRAM) structure, including a substrate and multiple MRAM cells on the substrate, wherein the MRAM cells are arranged in a memory region adjacent to a logic region. An ultra low-k (ULK) layer covers the MRAM cells, wherein the surface portion of ultra low-k layer is doped with fluorine, and dents are formed on the surface of ultra low-k layer at the boundaries between the memory region and the logic region.Type: GrantFiled: April 28, 2021Date of Patent: February 27, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Ching-Hua Hsu, Si-Han Tsai, Shun-Yu Huang, Chen-Yi Weng, Ju-Chun Fan, Che-Wei Chang, Yi-Yu Lin, Po-Kai Hsu, Jing-Yin Jhang, Ya-Jyuan Hung
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Patent number: 9911594Abstract: Methods for forming fin structure with desired materials formed on different locations of the fin structure using a selective deposition process for three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips are provided. In one embodiment, a method of forming a structure with desired materials on a substrate includes forming a patterned self-assembled monolayer on a circumference of a structure formed on a substrate, wherein the patterned self-assembled monolayer includes a treated layer formed among a self-assembled monolayer, and performing an atomic layer deposition process to form a material layer predominantly on the self-assembled monolayer from the patterned self-assembled monolayer.Type: GrantFiled: November 8, 2016Date of Patent: March 6, 2018Assignee: Applied Materials, Inc.Inventors: Srinivas D. Nemani, Ellie Y. Yieh, Ludovic Godet, Yin Fan
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Patent number: 9754791Abstract: Methods for selectively depositing different materials at different locations on a substrate are provided. A selective deposition process may form different materials on different surfaces, e.g., different portions of the substrate, depending on the material properties of the underlying layer being deposited on. Ion implantation processes may be used to modify materials disposed on the substrate. The ions modify surface properties of the substrate to enable the subsequent selective deposition process. A substrate having a mask disposed thereon may be subjected to an on implantation process to modify the mask and surfaces of the substrate exposed by the mask. The mask may be removed which results in a substrate having regions of implanted and non-implanted materials. A subsequent deposition process may be performed to selectively deposit on either the implanted or non-implanted regions of the substrate.Type: GrantFiled: April 7, 2015Date of Patent: September 5, 2017Assignee: APPLIED MATERIALS, INC.Inventors: Ludovic Godet, Yin Fan, Ellie Y. Yieh, Srinivas D. Nemani
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Publication number: 20170053797Abstract: Methods for forming fin structure with desired materials formed on different locations of the fin structure using a selective deposition process for three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips are provided. In one embodiment, a method of forming a structure with desired materials on a substrate includes forming a patterned self-assembled monolayer on a circumference of a structure formed on a substrate, wherein the patterned self-assembled monolayer includes a treated layer formed among a self-assembled monolayer, and performing an atomic layer deposition process to form a material layer predominantly on the self-assembled monolayer from the patterned self-assembled monolayer.Type: ApplicationFiled: November 8, 2016Publication date: February 23, 2017Inventors: Srinivas D. NEMANI, Ellie Y. YIEH, Ludovic GODET, Yin FAN
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Patent number: 9515166Abstract: Methods for forming fin structure with desired materials formed on different locations of the fin structure using a selective deposition process for three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips are provided. In one embodiment, a method of forming a structure with desired materials on a substrate includes forming a patterned self-assembled monolayer on a circumference of a structure formed on a substrate, wherein the patterned self-assembled monolayer includes a treated layer formed among a self-assembled monolayer, and performing an atomic layer deposition process to form a material layer predominantly on the self-assembled monolayer from the patterned self-assembled monolayer.Type: GrantFiled: May 13, 2014Date of Patent: December 6, 2016Assignee: APPLIED MATERIALS, INC.Inventors: Srinivas D. Nemani, Ellie Y. Yieh, Ludovic Godet, Yin Fan
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Publication number: 20160233100Abstract: Methods for selectively depositing different materials at diffe ent locations on a substrate are provided. A selective deposition process may form different materials on different surfaces, e.g., different portions of the substrate, depending on the material properties of the underlying layer being deposited on on implantation processes may be used to modify materials disposed on the substrate. The ions modify surface properties of the substrate to enable the subsequent selective deposition process. A substrate having a mask disposed thereon may be subjected to an on implantation process to modify the mask and surfaces of the substrate exposed by the mask. The mask may be removed which results in a substrate having regions of implanted and non-implanted materials. A subsequent deposition process may be performed to selectively deposit on either the implanted or non-implanted regions of the substrate.Type: ApplicationFiled: April 7, 2015Publication date: August 11, 2016Inventors: Ludovic GODET, Yin FAN, Ellie Y. YIEH, Srinivas D. NEMANI
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Patent number: 9385219Abstract: Methods for forming fin structures with desired materials formed on different locations of the fin structure using a selective deposition process for fin field effect transistors (FinFETs) are provided. In one embodiment, a method of forming a structure with desired materials on a substrate includes depositing a first material on a substrate having a three-dimensional (3D) structure formed thereon while performing an implantation process to dope a first region of the 3D structure. The first material may be removed and a second material may be deposited on the 3D structure. The second material may selectively grow on a second region of the 3D structure.Type: GrantFiled: June 29, 2015Date of Patent: July 5, 2016Assignee: APPLIED MATERIALS, INC.Inventors: Ellie Y. Yieh, Srinivas D. Nemani, Ludovic Godet, Yin Fan, Tristan Ma
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Publication number: 20160005839Abstract: Methods for forming fin structures with desired materials formed on different locations of the fin structure using a selective deposition process for fin field effect transistors (FinFETs) are provided. In one embodiment, a method of forming a structure with desired materials on a substrate includes depositing a first material on a substrate having a three-dimensional (3D) structure formed thereon while performing an implantation process to dope a first region of the 3D structure. The first material may be removed and a second material may be deposited on the 3D structure. The second material may selectively grow on a second region of the 3D structure.Type: ApplicationFiled: June 29, 2015Publication date: January 7, 2016Inventors: Ellie Y. YIEH, Srinivas D. NEMANI, Ludovic GODET, Yin FAN, Tristan MA
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Publication number: 20150294863Abstract: Methods for forming fin structure with desired materials formed on different locations of the fin structure using a selective deposition process for three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips are provided. In one embodiment, a method of forming a structure with desired materials on a substrate includes forming a patterned self-assembled monolayer on a circumference of a structure formed on a substrate, wherein the patterned self-assembled monolayer includes a treated layer formed among a self-assembled monolayer, and performing an atomic layer deposition process to form a material layer predominantly on the self-assembled monolayer from the patterned self-assembled monolayer.Type: ApplicationFiled: May 13, 2014Publication date: October 15, 2015Inventors: Srinivas D. NEMANI, Ellie Y. YIEH, Ludovic GODET, Yin FAN
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Patent number: 8228022Abstract: A solar energy control system includes a storage battery, a solar energy operated absorption board, a load, a controller, a first ZigBee module, a second ZigBee module, and a monitoring device. The absorption board is connected to the battery for charging the battery. The load is connected to the battery for receiving a working voltage from the battery. The controller is connected to the absorption board to detect a voltage of the absorption board, and control the charging status according to the detected voltage. The first ZigBee module is connected to the monitoring device. The second ZigBee module is connected to the controller. The monitoring device monitors a status of the controller and sends control instructions to the controller through the first and second ZigBee modules.Type: GrantFiled: March 4, 2008Date of Patent: July 24, 2012Assignee: Hon Hai Precision Industry Co., Ltd.Inventor: Yin-Fan Chen
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Publication number: 20090160395Abstract: A solar energy control system includes a storage battery, a solar energy operated absorption board, a load, a controller, a first ZigBee module, a second ZigBee module, and a monitoring device. The absorption board is connected to the battery for charging the battery. The load is connected to the battery for receiving a working voltage from the battery. The controller is connected to the absorption board to detect a voltage of the absorption board, and control the charging status according to the detected voltage. The first ZigBee module is connected to the monitoring device. The second ZigBee module is connected to the controller. The monitoring device monitors a status of the controller and sends control instructions to the controller through the first and second ZigBee modules.Type: ApplicationFiled: March 4, 2008Publication date: June 25, 2009Applicant: HON HAI PRECISION INDUSTRY CO., LTD.Inventor: YIN-FAN CHEN
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Publication number: 20080117439Abstract: An optical navigation system and method of estimating motion uses an optical structure configured to collimate light propagating along a first direction and to internally reflect the light off an output reflective surface of the optical structure downward along a second direction perpendicular to the first direction toward a target surface. The optical structure is also configured to transmit the light reflected from the target surface through the output reflective surface toward an image sensor.Type: ApplicationFiled: December 20, 2006Publication date: May 22, 2008Inventors: Yat Kheng Leong, Hun Kwang Lee, Sai Mun Lee, Gladys Su Yin Fan