Patents by Inventor Yin-Fu Huang
Yin-Fu Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9899513Abstract: A lateral diffused metal oxide semiconductor (LDMOS) transistor and a manufacturing method thereof are provided. A deep well region is disposed in a substrate. An isolation structure is disposed in the substrate to define a first active area and a second active area. A well region is disposed in the deep well region in the first active area. A gate is disposed on the substrate in the first active area. A gate dielectric layer is disposed between the gate and the substrate. A first doped region is disposed in the well region in the first active area and located at one side of the gate. A second doped region is disposed in the deep well region in the second active area. A conductive structure is disposed on the isolation structure, surrounds the second doped region and is connected to the gate.Type: GrantFiled: December 29, 2016Date of Patent: February 20, 2018Assignee: MACRONIX International Co., Ltd.Inventors: Wei-Chih Lin, Chih-Chia Hsu, Yin-Fu Huang
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Patent number: 9231078Abstract: A semiconductor element and a manufacturing method thereof are provided. The semiconductor element includes a base, an epitaxy layer, a first well, a second well, a third well, a first heavily doping region, a second heavily doping region, a implanting region and a conductive layer. The epitaxy layer is disposed on the base. The first well, the second well and the third well are disposed in the epitaxy layer. The third well is located between the first well and the second well. A surface channel is formed between the first heavily doping region and the second heavily doping region. The implanting region is fully disposed between the surface channel and the base and disposed at a projection region of the first well, the second well and the third well.Type: GrantFiled: December 5, 2012Date of Patent: January 5, 2016Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Miao-Chun Chung, Yin-Fu Huang, Shih-Chin Lien
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Patent number: 9082787Abstract: A semiconductor structure includes a substrate having a first conductive type, a well having a second conductive type formed in the substrate, a first doped region and a second doped region formed in the well, a field oxide, a first dielectric layer and a second dielectric layer. The field oxide is formed on a surface region of the well and between the first doped region and the second doped region. The first dielectric layer is formed on the surface region of the well and covers an edge portion of the field oxide. The first dielectric layer has a first thickness. The second dielectric layer is formed on the surface region of the well. The second dielectric layer has a second thickness smaller than the first thickness.Type: GrantFiled: December 23, 2013Date of Patent: July 14, 2015Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Yu-Hsien Chin, Chih-Chia Hsu, Yin-Fu Huang
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Patent number: 9029947Abstract: A field device and method of operating high voltage semiconductor device applied with the same are provided. The field device includes a first well having a second conductive type and second well having a first conductive type both formed in the substrate (having the first conductive type) and extending down from a surface of the substrate, the second well adjacent to one side of the first well and the substrate is at the other side of the first well; a first doping region having the first conductive type and formed in the second well, the first doping region spaced apart from the first well; a conductive line electrically connected to the first doping region and across the first well region; and a conductive body insulatively positioned between the conductive line and the first well, and the conductive body correspondingly across the first well region.Type: GrantFiled: October 21, 2014Date of Patent: May 12, 2015Assignee: Macronix International Co., Ltd.Inventors: An-Li Cheng, Miao-Chun Chung, Chih-Chia Hsu, Yin-Fu Huang
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Publication number: 20150035583Abstract: A field device and method of operating high voltage semiconductor device applied with the same are provided. The field device includes a first well having a second conductive type and second well having a first conductive type both formed in the substrate (having the first conductive type) and extending down from a surface of the substrate, the second well adjacent to one side of the first well and the substrate is at the other side of the first well; a first doping region having the first conductive type and formed in the second well, the first doping region spaced apart from the first well; a conductive line electrically connected to the first doping region and across the first well region; and a conductive body insulatively positioned between the conductive line and the first well, and the conductive body correspondingly across the first well region.Type: ApplicationFiled: October 21, 2014Publication date: February 5, 2015Inventors: An-Li Cheng, Miao-Chun Chung, Chih-Chia Hsu, Yin-Fu Huang
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Patent number: 8928095Abstract: A semiconductor device having a well, a p well implant bounded at least in part within a substrate by the well, a conductive layer disposed on the substrate, a high voltage n? (HVN?) doped well implanted in the p well implant, a high voltage p doped (HVPD) well implanted in the p well implant, and a drain n? well and a source n? well disposed in the HVN? doped well and HVPD well, respectively, is provided. A method of fabricating the semiconductor device is also provided. In certain embodiments, the method of fabricating the semiconductor device is characterized by implanting the HVN? ions at a first tilt angle and/or implanting the HVPD ions at a second tilt angle.Type: GrantFiled: August 16, 2013Date of Patent: January 6, 2015Assignee: Macronix International Co., Ltd.Inventors: Chien-Chung Chen, Ming-Tung Lee, Yin-Fu Huang, Shih-Chin Lien, Shyi-Yuan Wu
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Patent number: 8896061Abstract: A field device and method of operating high voltage semiconductor device applied with the same are provided. The field device includes a first well having a second conductive type and second well having a first conductive type both formed in the substrate (having the first conductive type) and extending down from a surface of the substrate, the second well adjacent to one side of the first well and the substrate is at the other side of the first well; a first doping region having the first conductive type and formed in the second well, the first doping region spaced apart from the first well; a conductive line electrically connected to the first doping region and across the first well region; and a conductive body insulatively positioned between the conductive line and the first well, and the conductive body correspondingly across the first well region.Type: GrantFiled: September 14, 2012Date of Patent: November 25, 2014Assignee: Macronix International Co., Ltd.Inventors: An-Li Cheng, Miao-Chun Chung, Chih-Chia Hsu, Yin-Fu Huang
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Publication number: 20140264599Abstract: A semiconductor device having a well, a p well implant bounded at least in part within a substrate by the well, a conductive layer disposed on the substrate, a high voltage n? (HVN?) doped well implanted in the p well implant, a high voltage p doped (HVPD) well implanted in the p well implant, and a drain n? well and a source n? well disposed in the HVN? doped well and HVPD well, respectively, is provided. A method of fabricating the semiconductor device is also provided. In certain embodiments, the method of fabricating the semiconductor device is characterized by implanting the HVN? ions at a first tilt angle and/or implanting the HVPD ions at a second tilt angle.Type: ApplicationFiled: August 16, 2013Publication date: September 18, 2014Applicant: Macronix International Co. Ltd.Inventors: Chien-Chung Chen, Ming-Tung Lee, Yin-Fu Huang, Shin-Chin Lien, Shyi-Yuan Wu
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Publication number: 20140175526Abstract: A semiconductor device where at least one of a portion of the first metal layer that extends from the source contact, a portion of the second metal layer that extends from the source contact, a portion of the first metal layer that extends from the drain contact, and a portion of the second metal layer that extends from the drain contact is configured to lie above a portion of or even all of the gate. Methods of fabricating and using such a semiconductor device are also provided.Type: ApplicationFiled: December 20, 2012Publication date: June 26, 2014Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Kuo Hung Hsieh, Meng Shien Hsieh, Yin Fu Huang, Miao Chun Chung
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Publication number: 20140151764Abstract: A semiconductor element and a manufacturing method thereof are provided. The semiconductor element includes a base, an epitaxy layer, a first well, a second well, a third well, a first heavily doping region, a second heavily doping region, a implanting region and a conductive layer. The epitaxy layer is disposed on the base. The first well, the second well and the third well are disposed in the epitaxy layer. The third well is located between the first well and the second well. A surface channel is formed between the first heavily doping region and the second heavily doping region. The implanting region is fully disposed between the surface channel and the base and disposed at a projection region of the first well, the second well and the third well.Type: ApplicationFiled: December 5, 2012Publication date: June 5, 2014Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Miao-Chun Chung, Yin-Fu Huang, Shih-Chin Lien
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Publication number: 20140106519Abstract: A semiconductor structure includes a substrate having a first conductive type, a well having a second conductive type formed in the substrate, a first doped region and a second doped region formed in the well, a field oxide, a first dielectric layer and a second dielectric layer. The field oxide is formed on a surface region of the well and between the first doped region and the second doped region. The first dielectric layer is formed on the surface region of the well and covers an edge portion of the field oxide. The first dielectric layer has a first thickness. The second dielectric layer is formed on the surface region of the well. The second dielectric layer has a second thickness smaller than the first thickness.Type: ApplicationFiled: December 23, 2013Publication date: April 17, 2014Applicant: Macronix International Co., Ltd.Inventors: Yu-Hsien Chin, Chih-Chia Hsu, Yin-Fu Huang
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Patent number: 8691653Abstract: A semiconductor structure and a manufacturing process thereof are disclosed. The semiconductor structure includes a substrate having a first conductive type, a first well having a second conductive type formed in the substrate, a doped region having the second conductive type formed in the first well, a field oxide and a second well having the first conductive type. The doped region has a first net dopant concentration. The field oxide is formed on a surface area of the first well. The second well is disposed underneath the field oxide and connected to a side of the doped region. The second well has a second net dopant concentration smaller than the first net dopant concentration.Type: GrantFiled: March 5, 2012Date of Patent: April 8, 2014Assignee: Macronix International Co., Ltd.Inventors: Chih-Chia Hsu, Yu-Hsien Chin, Yin-Fu Huang
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Publication number: 20140077866Abstract: A field device and method of operating high voltage semiconductor device applied with the same are provided. The field device includes a first well having a second conductive type and second well having a first conductive type both formed in the substrate (having the first conductive type) and extending down from a surface of the substrate, the second well adjacent to one side of the first well and the substrate is at the other side of the first well; a first doping region having the first conductive type and formed in the second well, the first doping region spaced apart from the first well; a conductive line electrically connected to the first doping region and across the first well region; and a conductive body insulatively positioned between the conductive line and the first well, and the conductive body correspondingly across the first well region.Type: ApplicationFiled: September 14, 2012Publication date: March 20, 2014Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: An-Li Cheng, Miao-Chun Chung, Chih-Chia Hsu, Yin-Fu Huang
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Patent number: 8659080Abstract: A semiconductor structure includes a substrate having a first conductive type, a well having a second conductive type formed in the substrate, a first doped region and a second doped region formed in the well, a field oxide, a first dielectric layer and a second dielectric layer. The field oxide is formed on a surface region of the well and between the first doped region and the second doped region. The first dielectric layer is formed on the surface region of the well and covers an edge portion of the field oxide. The first dielectric layer has a first thickness. The second dielectric layer is formed on the surface region of the well. The second dielectric layer has a second thickness smaller than the first thickness.Type: GrantFiled: March 5, 2012Date of Patent: February 25, 2014Assignee: Macronix International Co., Ltd.Inventors: Yu-Hsien Chin, Chih-Chia Hsu, Yin-Fu Huang
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Patent number: 8643072Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a bulk, a gate, a source, a drain and a bulk contact region. The gate is on the bulk. The source and the drain are in the bulk on opposing sides of the gate respectively. The bulk contact region is only in a region of the bulk adjacent to the source. The bulk contact region is electrically connected to the bulk.Type: GrantFiled: July 12, 2012Date of Patent: February 4, 2014Assignee: Macronix International Co., Ltd.Inventors: Miao-Chun Chung, An-Li Cheng, Yin-Fu Huang, Shih-Chin Lien, Shyi-Yuan Wu
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Publication number: 20140015016Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a bulk, a gate, a source, a drain and a bulk contact region. The gate is on the bulk. The source and the drain are in the bulk on opposing sides of the gate respectively. The bulk contact region is only in a region of the bulk adjacent to the source. The bulk contact region is electrically connected to the bulk.Type: ApplicationFiled: July 12, 2012Publication date: January 16, 2014Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Miao-Chun Chung, An-Li Cheng, Yin-Fu Huang, Shih-Chin Lien, Shyi-Yuan Wu
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Patent number: 8586442Abstract: A manufacturing method for a high voltage transistor includes the following steps. A substrate is provided. A P-type epitaxial (P-epi) layer is provided above the substrate. An N-well is formed in the P-epi layer. A P-well is formed in the P-epi layer. Field oxide (FOX) layers are formed above the P-epi layer. A gate oxide (GOX) layer is formed between the FOX layers. P-type implants are doped into the P-well or N-type implants are doped into the N-well to adjust an electrical function of the high voltage transistor.Type: GrantFiled: November 28, 2012Date of Patent: November 19, 2013Assignee: Macronix International Co. Ltd.Inventors: Yu-Hsien Chin, Chih-Chia Hsu, Yin-Fu Huang
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Publication number: 20130228861Abstract: A semiconductor structure and a manufacturing process thereof are disclosed. The semiconductor structure includes a substrate having a first conductive type, a first well having a second conductive type formed in the substrate, a doped region having the second conductive type formed in the first well, a field oxide and a second well having the first conductive type. The doped region has a first net dopant concentration. The field oxide is formed on a surface area of the first well. The second well is disposed underneath the field oxide and connected to a side of the doped region. The second well has a second net dopant concentration smaller than the first net dopant concentration.Type: ApplicationFiled: March 5, 2012Publication date: September 5, 2013Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chih-Chia Hsu, Yu-Hsien Chin, Yin-Fu Huang
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Publication number: 20130228831Abstract: A semiconductor structure includes a substrate having a first conductive type, a well having a second conductive type formed in the substrate, a first doped region and a second doped region formed in the well, a field oxide, a first dielectric layer and a second dielectric layer. The field oxide is formed on a surface region of the well and between the first doped region and the second doped region. The first dielectric layer is formed on the surface region of the well and covers an edge portion of the field oxide. The first dielectric layer has a first thickness. The second dielectric layer is formed on the surface region of the well. The second dielectric layer has a second thickness smaller than the first thickness.Type: ApplicationFiled: March 5, 2012Publication date: September 5, 2013Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Yu-Hsien Chin, Chih-Chia Hsu, Yin-Fu Huang
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Patent number: 8507993Abstract: Various aspects of the technology are directed to integrated circuit manufacturing methods and integrated circuits. In one method, a first charge type buried layer in a semiconductor material of an integrated circuit by implanting first charge type dopants of the first charge type buried layer through a sacrificial oxide over the semiconductor material and through an intermediate region of the semiconductor material transited by the implanted first charge type dopants. When the implanted dopants pass through the sacrificial oxide, damage to the semiconductor crystalline lattice is averted. If the sacrificial oxide were absent, the implanted dopants would have passed through and damaged the semiconductor crystalline lattice instead. Later, a pre-anneal oxide is grown and removed.Type: GrantFiled: August 28, 2012Date of Patent: August 13, 2013Assignee: Macronix International Co., Ltd.Inventors: Yin-Fu Huang, Ming Rong Chang, Shih-Chin Lien