Patents by Inventor Yin Hu

Yin Hu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6196093
    Abstract: A hand-held tool handle reflects to a handle with a hollow body, and the character is that the hollow body is in a longitudinal direction with an opening at one side of the handle. The inner hollow portion has a spring push button which has one end remained in the hollow body while the other end extending outwardly from the opening. The hollow body is mounted with a tool holder which has formed with a number of seats to receive bits thereat. The center portion of the tool holder has a strut corresponding to the push button, by pushing the push button, the tool holder will extend outwardly, and the bits may be picked for prompt usage.
    Type: Grant
    Filed: June 4, 1999
    Date of Patent: March 6, 2001
    Inventor: Cheng-Yin Hu
  • Patent number: 6083809
    Abstract: A method of fabricating a semiconductor device and the device which includes initially providing a layer of silicon having a thin oxide layer thereon and a patterned layer of a masking material not permeable to at least selected oxygen-bearing species and having a sidewall disposed over said oxide layer to provide an exposed intersection of the masking material and the oxide layer. An oxygen-bearing species conductive path is then formed on the sidewall of the masking material extending to the exposed intersection for conducting the selected oxygen-bearing species. A sidewall layer of a material different from the conductive path is formed on the conductive path. An oxygen-bearing species is then applied to the exposed intersection through the path and a thick oxide surrounding the masking material is fabricated concurrently or as a separate step. The masking material is preferably silicon nitride, the path is preferably silicon oxide and the sidewall layer is preferably silicon nitride.
    Type: Grant
    Filed: October 1, 1997
    Date of Patent: July 4, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: William F. Richardson, Yin Hu
  • Patent number: 5936278
    Abstract: A semiconductor over insulator transistor (100) includes a semiconductor mesa (36) formed over an insulating layer (34) which overlies a semiconductor substrate (32). Source and drain regions (66, 68) of a first conductivity type are formed at opposite ends of the mesa. A body node (56) of a second conductivity type is located between the source and drain regions in the mesa. A gate insulator (40) and a gate electrode (46) lie over the body node. Halo implants (54, 56) are placed to completely separate the source and drain regions from the body node, or channel regions, for improving short channel effect. The transistor is useful as a pass gate and as a peripheral transistor in a DRAM, and also is useful in digital and analog applications and in low power applications.
    Type: Grant
    Filed: March 7, 1997
    Date of Patent: August 10, 1999
    Assignee: Texas Instruments Incorporated
    Inventors: Yin Hu, Jarvis B. Jacobs, Theodore W. Houston
  • Patent number: 5910017
    Abstract: A technique of producing a semiconductor device or integrated circuit produces a planarized refill layer which has a more uniform thickness after etch back. In a silicon-on-insulator (SOI) device, dummy active areas are inserted between the active areas in order to maintain the thickness of the refill layer between the mesas to insure proper isolation between the active devices. The technique is also applicable to non-SOI devices.
    Type: Grant
    Filed: February 21, 1997
    Date of Patent: June 8, 1999
    Assignee: Texas Instruments Incorporated
    Inventor: Yin Hu
  • Patent number: 5909628
    Abstract: A technique of producing a semiconductor device or integrated circuit produces a planarized refill layer which has a more uniform thickness after polishing, such as by chemical-mechanical polishing (CMP). Dummy active areas are inserted between active areas in that portion of the substrate which would normally be occupied by a field oxide in order to reduce to "dishing" that occurs during CMP in these areas. The dummy active areas can take the shape of a large block, a partially or completely formed ring structure or a plurality of pillars the area density of which can be adjusted to match the area density of the active areas in that region of the substrate. The design rule for the pillars can be such that no pillars are placed where polycrystalline silicon lines or first level metallization lines are to be placed in order to avoid parasitic capacitances.
    Type: Grant
    Filed: February 21, 1997
    Date of Patent: June 1, 1999
    Assignee: Texas Instruments Incorporated
    Inventors: Amitava Chatterjee, Theodore W. Houston, Ih-Chin Chen, Agerico L. Esquirel, Somnath Nag, Iqbal Ali, Keith A. Joyner, Yin Hu, Jeffrey Alan McKee, Peter Stewart McAnally