Patents by Inventor Yin Jen Chen
Yin Jen Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240156413Abstract: An apparatus and a method for detecting heartbeat include a sensor configured to detect displacements of an object without contacting the object wherein the object displaces corresponding the a human's heartbeat, a data processing unit configured to extract a feature dataset from the detected displacement data, and a neural network configured to inference inter beat intervals from the extracted feature dataset using a pre-trained model.Type: ApplicationFiled: November 8, 2022Publication date: May 16, 2024Applicant: WISTRON CORPORATIONInventors: Yin-Yu CHEN, Kai Jen CHENG, Yao-Tsung CHANG
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Patent number: 11322207Abstract: A program method for a memory device is provided. The memory device includes a plurality of memory cells, a bit line and word lines electrically connected to the plurality of memory cells. The plurality of memory cells includes a selected memory cell and unselected memory cells when the memory device is in a program operation. The program method including performing precharge steps, performing program steps and performing a verification step to the selected memory cell after the precharge steps and the program steps. Each of the precharge steps includes applying a precharge voltage to the bit line electrically connected to the unselected memory cells. Each of the program steps includes applying a program voltage to a word line of the word lines electrically connected to the selected memory cell.Type: GrantFiled: December 30, 2020Date of Patent: May 3, 2022Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Cheng-Hsien Cheng, Yu-Hung Huang, Chia-Hong Lee, Yin-Jen Chen
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Patent number: 11289132Abstract: The present invention discloses an operation method of memory device, applied to a memory device including a number of word lines and one or more functional lines. The operation method includes: receiving a read command for a target memory cell of the memory device; and outputting a signal having a first waveform to a target word line corresponding to the target memory cell to be read among a plurality of the word lines of the memory device, output a signal having a second waveform to the one or more functional lines of the memory device, and output a signal having a third waveform to the word lines other than the target word line. A falling time of the third waveform is longer than a falling time of the first waveform.Type: GrantFiled: February 5, 2021Date of Patent: March 29, 2022Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Yu-Hung Huang, Cheng-Hsien Cheng, Chih-Chieh Cheng, Yin-Jen Chen
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Patent number: 10796753Abstract: A method for determining quick-pass-write (QPW) operation in increment-step-program-pulse (ISPP) operation is provided. The QPW operation is simultaneously applying a bit line voltage during the ISPP operation. The method includes, according to bit line voltages varying in a first range and voltage difference values varying in a second range with respect to a verified voltage, estimating a shrinkage quantity of threshold voltage distribution width at each bit line voltage and each voltage difference value, so as to obtain a shrinkage-quantity topographic contour. According to the bit line voltages and the voltage difference values, a program shot number as needed to achieve the verified voltage is estimated, so as to obtain a program-shot-number topographic contour.Type: GrantFiled: October 29, 2019Date of Patent: October 6, 2020Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Yu-Hung Huang, Cheng-Hsien Cheng, Shaw-Hung Ku, Yin-Jen Chen
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Patent number: 9466371Abstract: A transistor is described including a fly-over conductor. The transistor has a gate, a channel and a source/drain terminal. The fly-over conductor is disposed over the source/drain terminal. A circuit is connected to the fly-over conductor to apply a bias voltage tending to offset effects on the transistor of charge trapped in insulating material. A word line driver can include a transistor with a fly-over conductor.Type: GrantFiled: July 29, 2014Date of Patent: October 11, 2016Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Yi-Peng Chang, Yin-Jen Chen
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Publication number: 20160035422Abstract: A transistor is described including a fly-over conductor. The transistor has a gate, a channel and a source/drain terminal. The fly-over conductor is disposed over the source/drain terminal. A circuit is connected to the fly-over conductor to apply a bias voltage tending to offset effects on the transistor of charge trapped in insulating material. A word line driver can include a transistor with a fly-over conductor.Type: ApplicationFiled: July 29, 2014Publication date: February 4, 2016Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: YI-PENG CHANG, YIN-JEN CHEN
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Patent number: 9036393Abstract: A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.Type: GrantFiled: October 25, 2013Date of Patent: May 19, 2015Assignee: MACRONIX International Co., Ltd.Inventors: Kuan-Fu Chen, Yin-Jen Chen, Tzung-Ting Han, Ming-Shang Chen
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Publication number: 20140050006Abstract: A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.Type: ApplicationFiled: October 25, 2013Publication date: February 20, 2014Applicant: MACRONIX International Co., Ltd.Inventors: Kuan-Fu Chen, Yin-Jen Chen, Tzung-Ting Han, Ming-Shang Chen
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Patent number: 8593850Abstract: A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.Type: GrantFiled: December 30, 2008Date of Patent: November 26, 2013Assignee: MACRONIX International Co., Ltd.Inventors: Kuan-Fu Chen, Yin-Jen Chen, Tzung-Ting Han, Ming-Shang Chen
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Patent number: 8552528Abstract: A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.Type: GrantFiled: September 22, 2011Date of Patent: October 8, 2013Assignee: Macronix International Co., Ltd.Inventors: Kuan-Fu Chen, Yin-Jen Chen, Tzung-Ting Han, Ming Shang Chen
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Patent number: 8330232Abstract: A multi-bit memory cell includes a substrate; a multi-bit charge-trapping cell over the substrate, the multi-bit charge-trapping cell having a first lateral side and a second lateral side; a source region in the substrate, a portion of the source region being under the first side of the multi-bit charge-trapping cell; a drain region in the substrate, a portion of the drain region being under the second side of the multi-bit charge-trapping cell; and a channel region in the substrate between the source region and the drain region. The channel region has one of a p-type doping and an n-type doping, and the doping is configured to provide a highest doping concentration near the central portion of the channel region.Type: GrantFiled: August 22, 2005Date of Patent: December 11, 2012Assignee: MACRONIX International Co., Ltd.Inventors: Shao Hong Ku, Yin Jen Chen, Wenpin Lu, Tahui Wang
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Patent number: 8183106Abstract: A method for fabricating a floating gate memory device comprises using self-aligned process for formation of a fourth poly layer over a partial gate structure that does not require an additional photolithographic step. Accordingly, enhanced device reliability can be achieved because a higher GCR can be maintained with lower gate bias levels. In addition, process complexity can be reduced, which can increase throughput and reduce device failures.Type: GrantFiled: July 26, 2006Date of Patent: May 22, 2012Assignee: Macronix International Co., Ltd.Inventors: Kuan Fu Chen, Yin Jen Chen, Meng Hsuan Weng, Tzung Ting Han, Ming Shang Chen, Chun Pei Wu
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Patent number: 8111547Abstract: A multi-bit flash memory and a reading method thereof. Multiple reference memory cells for saving reserved data are provided to operate together with multiple data memory cells. Before the data memory cells are read, data stored in the reference memory cell is sensed based on a present reference current. Then, a value of a new reference current for reading the data memory cells is determined according to a difference between the sensed data and the reserved data.Type: GrantFiled: December 11, 2009Date of Patent: February 7, 2012Assignee: Macronix International Co., Ltd.Inventors: Yung-Feng Lin, Nian-Kai Zous, I-Jen Huang, Yin-Jen Chen
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Publication number: 20120008363Abstract: A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.Type: ApplicationFiled: September 22, 2011Publication date: January 12, 2012Applicant: Macronix International Co., Ltd.Inventors: Kuan-Fu Chen, Yin-Jen Chen, Tzung-Ting Han, Ming Shang Chen
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Patent number: 7888272Abstract: A semiconductor fabrication process allows the fabrication of both logic and memory devices using a conventional CMOS process with a few additional steps. The additional steps, however, do not require additional masks. Accordingly, the process can be reduce the complexity, time, and cost for fabricating logic and memory devices on the same substrate, especially for embedded applications.Type: GrantFiled: December 12, 2006Date of Patent: February 15, 2011Assignee: Macronix International Co. Ltd.Inventors: Kuan Fu Chen, Yin Jen Chen, Tzung Ting Han, Ming-Shang Chen, Shih Chin Lee
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Patent number: 7710774Abstract: A NAND type multi-bit charge storage memory array comprises a first and a second memory strings each of which includes one or more charge storage memory cells and two select transistors. The charge storage memory cells are connected in series to form a memory cell string. The two select transistors are connected in series to both ends of the memory cell string, respectively. The NAND type multi-bit charge storage memory array further comprises a shared bit line and a first and a second bit lines. The shared bit line is connected with the first ends of the first and the second memory strings. The first and the second bit lines are connected to the second ends of the first and the second memory strings, respectively. The first select transistor and the second select transistor of each memory string are controlled by a first and a second select transistor control lines, respectively.Type: GrantFiled: November 23, 2005Date of Patent: May 4, 2010Assignee: Macronix International Co., Ltd.Inventors: Yin Jen Chen, Chun Lein Su, Ming Shiang Chin, Chih Chieh Yeh, Tzung Ting Han
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Publication number: 20100085809Abstract: A multi-bit flash memory and a reading method thereof. Multiple reference memory cells for saving reserved data are provided to operate together with multiple data memory cells. Before the data memory cells are read, data stored in the reference memory cell is sensed based on a present reference current. Then, a value of a new reference current for reading the data memory cells is determined according to a difference between the sensed data and the reserved data.Type: ApplicationFiled: December 11, 2009Publication date: April 8, 2010Applicant: MACRONIX INTERNATIONAL CO. LTD.Inventors: Yung-Feng LIN, Nian-Kai Zous, I-Jen Huang, Yin-Jen Chen
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Patent number: 7643337Abstract: A multi-bit flash memory and a reading method thereof. Multiple reference memory cells for saving reserved data are provided to operate together with multiple data memory cells. Before the data memory cells are read, data stored in the reference memory cell is sensed based on a present reference current. Then, a value of a new reference current for reading the data memory cells is determined according to a difference between the sensed data and the reserved data.Type: GrantFiled: July 17, 2007Date of Patent: January 5, 2010Assignee: Macronix International Co., Ltd.Inventors: Yung-Feng Lin, Nian-Kai Zous, I-Jen Huang, Yin-Jen Chen
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Patent number: 7592036Abstract: A method for manufacturing a NAND flash memory is provided. First, a substrate is provided. Next, a tunneling dielectric layer, a first conductive layer and a mask layer are sequentially formed on the substrate. Next, a plurality of isolation structures is formed in the mask layer, the first conductive layer, the tunneling dielectric layer and the substrate. Next, the mask layer is removed, so that the top surface of each isolation structure is higher than that of the first conductive layer. Next, a second conductive layer is formed on the exposed sidewalls of the isolation structures. Next, an inter-gate dielectric layer and a third conductive layer are sequentially formed on the substrate.Type: GrantFiled: May 16, 2006Date of Patent: September 22, 2009Assignee: MACRONIX International Co., Ltd.Inventors: Kuei-Yun Chen, Chun-Lien Su, Yin-Jen Chen, Ming-Shang Chen
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Patent number: RE46970Abstract: A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.Type: GrantFiled: July 11, 2016Date of Patent: July 24, 2018Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Kuan-Fu Chen, Yin-Jen Chen, Tzung-Ting Han, Ming-Shang Chen