Patents by Inventor Yinan Shen
Yinan Shen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10262096Abstract: Systems and methods are disclosed herein to provide improved placement of components in programmable logic devices (PLDs). In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a PLD. The method also includes determining a layout comprising positions of components of the PLD configured to perform the operations. The method also includes performing a timing analysis on the layout. The method also includes selectively adjusting the positions of the components using the timing analysis. Related systems and non-transitory machine-readable mediums are also provided.Type: GrantFiled: February 28, 2014Date of Patent: April 16, 2019Assignee: Lattice Semiconductor CorporationInventors: Yinan Shen, Jun Zhao
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Publication number: 20150248512Abstract: Systems and methods are disclosed herein to provide improved placement of components in programmable logic devices (PLDs). In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a PLD. The method also includes determining a layout comprising positions of components of the PLD configured to perform the operations. The method also includes performing a timing analysis on the layout. The method also includes selectively adjusting the positions of the components using the timing analysis. Related systems and non-transitory machine-readable mediums are also provided.Type: ApplicationFiled: February 28, 2014Publication date: September 3, 2015Applicant: Lattice Semiconductor CorporationInventors: Yinan Shen, Jun Zhao
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Publication number: 20150178436Abstract: Various techniques are provided to perform clock assignments in a programmable logic device (PLD). In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a programmable logic device (PLD), synthesizing the design into a plurality of components of the PLD configured to perform the operations, and performing a simulated annealing process to determine a layout of the components in the PLD based on a system cost including a clock assignment cost for global clock signals of the PLD. Additional methods, systems, machine-readable mediums, and other techniques are also provided.Type: ApplicationFiled: December 20, 2013Publication date: June 25, 2015Applicant: LATTICE SEMICONDUCTOR CORPORATIONInventors: CHIH-CHUNG CHEN, JUN ZHAO, YINAN SHEN
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Patent number: 8112731Abstract: Techniques are provided for reducing signal congestion in programmable logic devices (PLDs). In one example, a computer-implemented method of reducing signal congestion in a configuration of a PLD includes mapping a plurality of circuit components of a circuit design to a plurality of components of the PLD, wherein each of the mapped PLD components is associated with one of a plurality of regions of the PLD and with one or more unique signal paths entering the PLD region. The method also includes determining a cost value for each PLD region based at least in part on the number of unique signal paths entering the PLD region from other PLD regions. The method also includes selecting one of the PLD components to move from a first one of the PLD regions to a second one of the PLD regions. The method also includes updating the cost values associated with the first and second PLD regions based on a change in the number of unique signal paths entering the first and second PLD regions.Type: GrantFiled: November 24, 2008Date of Patent: February 7, 2012Assignee: Lattice Semiconductor CorporationInventors: Yinan Shen, Chih-Chung Chen, Bo Wang
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Patent number: 8086986Abstract: In one embodiment of the invention, a programmable logic device (PLD) includes logic blocks, registers corresponding to the logic blocks, and configuration memory adapted to store configuration data for configuring the PLD. Also included in the PLD is a general routing network having a plurality of routing wires and a clock distribution network having a plurality of routing wires. At least one clock signal path is provided within the PLD from a clock source to one of the registers via a routing wire of the clock distribution network and a routing wire of the general routing network.Type: GrantFiled: March 20, 2009Date of Patent: December 27, 2011Assignee: Lattice Semiconductor CorporationInventors: Yinan Shen, Song Xu
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Patent number: 7509598Abstract: Systems and methods are disclosed herein to provide software clock boosting techniques. For example in one embodiment, a method of configuring a programmable logic device includes receiving routed data; performing a software clock boost operation on the routed data to determine and include one or more desired clock delays for circuit elements. The software clock boost operation may include performing a static timing analysis on the routed data; determining a list of the desired clock delays; and modifying the routed data to insert the desired clock delays.Type: GrantFiled: April 19, 2007Date of Patent: March 24, 2009Assignee: Lattice Semiconductor CorporationInventors: Yinan Shen, Song Xu
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Patent number: 7000210Abstract: A technique for mapping a plurality of configurable logic blocks in a programmable logic device, such as a field-programmable gate array (FPGA). The method includes adaptively adjusting one or more customer-specified constraints and can be implemented, for example, using a simulated annealing algorithm. During the refinement of the placement (i.e., assignment) of logic blocks in an FPGA, one or more constraints are adjusted by either selecting a customer-specified constraint value or specifying a new constraint value derived based on the actual circuit performance. The method provides substantial savings of computer time compared to the prior art placement methods and improves circuit performance, e.g., by enabling higher circuit operation frequencies.Type: GrantFiled: November 5, 2002Date of Patent: February 14, 2006Assignee: Lattice Semiconductor CorporationInventors: Qinghong Wu, Yinan Shen
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Patent number: 6813754Abstract: A method for placing configurable logic blocks (CLBs) in a PLD, such as an FPGA. In one embodiment, after packing gates/clusters into blocks and then assigning those blocks to CLBs to generate an initial placement, the packing and/or placement of CLBs is changed prior to performing CLB routing. For each node of the most critical of the K most critical paths in the initial placement, moving the node to a different CLB is considered in order to reduce the criticality of that path. A move is applied if certain acceptability conditions are met. After the most critical path is improved, the criticality of the K paths is updated, and the procedure is repeated for the new most critical of the K updated paths. The method, which can be automated to reduce human intervention in the design process, improves circuit performance, e.g., by enabling higher circuit operation frequencies.Type: GrantFiled: November 5, 2002Date of Patent: November 2, 2004Assignee: Lattice Semiconductor CorporationInventors: Qinghong Wu, Yinan Shen, Liren Liu
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Publication number: 20040088671Abstract: A technique for mapping a plurality of configurable logic blocks in a programmable logic device, such as a field-programmable gate array (FPGA). The method includes adaptively adjusting one or more customer-specified constraints and can be implemented, for example, using a simulated annealing algorithm. During the refinement of the placement (i.e., assignment) of logic blocks in an FPGA, one or more constraints are adjusted by either selecting a customer-specified constraint value or specifying a new constraint value derived based on the actual circuit performance. The method provides substantial savings of computer time compared to the prior art placement methods and improves circuit performance, e.g., by enabling higher circuit operation frequencies.Type: ApplicationFiled: November 5, 2002Publication date: May 6, 2004Inventors: Qinghong Wu, Yinan Shen
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Publication number: 20040088663Abstract: A method for placing configurable logic blocks (CLBs) in a PLD, such as an FPGA. In one embodiment, after packing gates/clusters into blocks and then assigning those blocks to CLBs to generate an initial placement, the packing and/or placement of CLBs is changed prior to performing CLB routing. For each node of the most critical of the K most critical paths in the initial placement, moving the node to a different CLB is considered in order to reduce the criticality of that path. A move is applied if certain acceptability conditions are met. After the most critical path is improved, the criticality of the K paths is updated, and the procedure is repeated for the new most critical of the K updated paths. The method, which can be automated to reduce human intervention in the design process, improves circuit performance, e.g., by enabling higher circuit operation frequencies.Type: ApplicationFiled: November 5, 2002Publication date: May 6, 2004Inventors: Qinghong Wu, Yinan Shen, Liren Liu