Patents by Inventor Ying-Chen LIU
Ying-Chen LIU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240153769Abstract: A first mask and a second mask are sequentially provided to perform a multi-step exposure and development processes. Through proper overlay design of the first mask and the second mask, conductive wirings having acceptable overlay offset are formed.Type: ApplicationFiled: January 17, 2024Publication date: May 9, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jie Chen, Hsien-Wei Chen, Tzuan-Horng Liu, Ying-Ju Chen
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Patent number: 11966170Abstract: A method includes receiving a wafer, measuring a surface topography of the wafer; calculating a topographical variation based on the surface topography measurement performing a single-zone alignment compensation when the topographical variation is less than a predetermined value or performing a multi-zone alignment compensation when the topographical variation is greater than the predetermined value; and performing a wafer alignment according to the single-zone alignment compensation or the multi-zone alignment compensation.Type: GrantFiled: October 27, 2020Date of Patent: April 23, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Ai-Jen Hung, Yung-Yao Lee, Heng-Hsin Liu, Chin-Chen Wang, Ying Ying Wang
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Publication number: 20240030338Abstract: A semiconductor device includes an active layer having first and second active regions, first and second source electrodes, first and second drain electrodes, first and second gate electrodes, a first source metal layer, first and second drain metal layers, and a source pad electrically connected to the first source metal layer. The second drain metal layer is electrically connected to the second drain electrode and the first source metal layer. A projection of the second drain metal layer on the active layer forms a drain metal layer region. An projection of the source pad on the active layer forms a source pad region. An area of an overlapping region between the source pad region and the drain metal layer region is smaller than or equal to 40% of an area of the drain metal layer region.Type: ApplicationFiled: October 6, 2023Publication date: January 25, 2024Inventors: Li-Fan LIN, Chun-Chieh YANG, Ying-Chen LIU
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Patent number: 11817494Abstract: A semiconductor device includes an active layer having an active region, a source electrode, a drain electrode, a gate electrode, a source metal layer, a drain metal layer, and a source pad. The source metal layer and the drain metal layer are electrically connected to the source electrode and the drain electrode, respectively. An orthogonal projection of the drain metal layer on the active layer each forms a drain metal layer region. The source pad is electrically connected to the source metal layer. An orthogonal projection of the source pad on the active layer forms a source pad region overlapping the drain metal layer. An area of an overlapping region between the source pad region and the drain metal layer region is smaller than or equal to 40% of an area of the drain metal layer region.Type: GrantFiled: December 14, 2020Date of Patent: November 14, 2023Assignee: ANCORA SEMICONDUCTORS INC.Inventors: Li-Fan Lin, Chun-Chieh Yang, Ying-Chen Liu
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Patent number: 11127845Abstract: A semiconductor structure is provided, which includes a semiconductor device, a first conductive layer, and a gate runner. The semiconductor device includes an upper surface, a gate terminal, a source terminal, and a drain terminal. The first conductive layer is deposited on the upper surface and coupled to the source terminal. The gate runner is overlapped with the first conductive layer and coupled to the gate terminal. The gate runner and the first conductive layer are configured to contribute a parasitic capacitance between the gate terminal and the source terminal.Type: GrantFiled: December 7, 2018Date of Patent: September 21, 2021Assignee: DELTA ELECTRONICS, INC.Inventors: Wen-Chia Liao, Ying-Chen Liu, Chen-Ting Chiang
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Publication number: 20210098617Abstract: A semiconductor device includes an active layer having an active region, a source electrode, a drain electrode, a gate electrode, a source metal layer, a drain metal layer, and a source pad. The source metal layer and the drain metal layer are electrically connected to the source electrode and the drain electrode, respectively. An orthogonal projection of the drain metal layer on the active layer each forms a drain metal layer region. The source pad is electrically connected to the source metal layer. An orthogonal projection of the source pad on the active layer forms a source pad region overlapping the drain metal layer. An area of an overlapping region between the source pad region and the drain metal layer region is smaller than or equal to 40% of an area of the drain metal layer region.Type: ApplicationFiled: December 14, 2020Publication date: April 1, 2021Inventors: Li-Fan LIN, Chun-Chieh YANG, Ying-Chen LIU
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Patent number: 10910491Abstract: A semiconductor device includes an active layer having an active region, a source electrode, a drain electrode, a gate electrode, a source metal layer, a drain metal layer, and a source pad. The source metal layer and the drain metal layer are electrically connected to the source electrode and the drain electrode, respectively. An orthogonal projection of the drain metal layer on the active layer each forms a drain metal layer region. The source pad is electrically connected to the source metal layer. An orthogonal projection of the source pad on the active layer forms a source pad region overlapping the drain metal layer. An area of an overlapping region between the source pad region and the drain metal layer region is smaller than or equal to 40% of an area of the drain metal layer region.Type: GrantFiled: August 26, 2019Date of Patent: February 2, 2021Assignee: DELTA ELECTRONICS, INC.Inventors: Li-Fan Lin, Chun-Chieh Yang, Ying-Chen Liu
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Patent number: 10833185Abstract: A semiconductor device includes an active layer, a source electrode, a drain electrode, a gate electrode, a source pad, a drain pad, and a source external connecting element. The source electrode, the drain electrode, and the gate electrode are disposed on an active region of the active layer. The source pad is electrically connected to the source electrode and includes a body portion, a plurality of branch portions, and a current diffusion portion. The body portion is at least partially disposed on the active region of the active layer. The current diffusion portion interconnects the body portion and the branch portions. A width of the current diffusion portion is greater than a width of the branch portion and less than a half of a width of the body portion. The source external connecting element is disposed on the body portion and spaced from the current diffusion portion.Type: GrantFiled: August 15, 2017Date of Patent: November 10, 2020Assignee: DELTA ELECTRONICS, INC.Inventors: Wen-Chia Liao, Ying-Chen Liu, Chen-Ting Chiang
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Patent number: 10680090Abstract: A semiconductor structure is provided, which includes a semiconductor device, a first conductive layer, and a gate runner. The semiconductor device includes an upper surface, a gate terminal, a source terminal, and a drain terminal. The first conductive layer is deposited on the upper surface and coupled to the source terminal. The gate runner is overlapped with the first conductive layer and coupled to the gate terminal. The gate runner and the first conductive layer are configured to contribute a parasitic capacitance between the gate terminal and the source terminal.Type: GrantFiled: July 20, 2017Date of Patent: June 9, 2020Assignee: DELTA ELECTRONICS, INC.Inventors: Wen-Chia Liao, Ying-Chen Liu, Chen-Ting Chiang
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Publication number: 20190386128Abstract: A semiconductor device includes an active layer having an active region, a source electrode, a drain electrode, a gate electrode, a source metal layer, a drain metal layer, and a source pad. The source metal layer and the drain metal layer are electrically connected to the source electrode and the drain electrode, respectively. An orthogonal projection of the drain metal layer on the active layer each forms a drain metal layer region. The source pad is electrically connected to the source metal layer. An orthogonal projection of the source pad on the active layer forms a source pad region overlapping the drain metal layer. An area of an overlapping region between the source pad region and the drain metal layer region is smaller than or equal to 40% of an area of the drain metal layer region.Type: ApplicationFiled: August 26, 2019Publication date: December 19, 2019Inventors: Li-Fan LIN, Chun-Chieh YANG, Ying-Chen LIU
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Publication number: 20190109221Abstract: A semiconductor structure is provided, which includes a semiconductor device, a first conductive layer, and a gate runner. The semiconductor device includes an upper surface, a gate terminal, a source terminal, and a drain terminal. The first conductive layer is deposited on the upper surface and coupled to the source terminal. The gate runner is overlapped with the first conductive layer and coupled to the gate terminal. The gate runner and the first conductive layer are configured to contribute a parasitic capacitance between the gate terminal and the source terminal.Type: ApplicationFiled: December 7, 2018Publication date: April 11, 2019Inventors: Wen-Chia LIAO, Ying-Chen LIU, Chen-Ting CHIANG
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Publication number: 20190027593Abstract: A semiconductor structure is provided, which includes a semiconductor device, a first conductive layer, and a gate runner. The semiconductor device includes an upper surface, a gate terminal, a source terminal, and a drain terminal. The first conductive layer is deposited on the upper surface and coupled to the source terminal. The gate runner is overlapped with the first conductive layer and coupled to the gate terminal. The gate runner and the first conductive layer are configured to contribute a parasitic capacitance between the gate terminal and the source terminal.Type: ApplicationFiled: July 20, 2017Publication date: January 24, 2019Inventors: Wen-Chia LIAO, Ying-Chen LIU, Chen-Ting CHIANG
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Publication number: 20180026125Abstract: A semiconductor device includes an active layer, a source electrode, a drain electrode, a gate electrode, a source pad, a drain pad, and a source external connecting element. The source electrode, the drain electrode, and the gate electrode are disposed on an active region of the active layer. The source pad is electrically connected to the source electrode and includes a body portion, a plurality of branch portions, and a current diffusion portion. The body portion is at least partially disposed on the active region of the active layer. The current diffusion portion interconnects the body portion and the branch portions. A width of the current diffusion portion is greater than a width of the branch portion and less than a half of a width of the body portion. The source external connecting element is disposed on the body portion and spaced from the current diffusion portion.Type: ApplicationFiled: August 15, 2017Publication date: January 25, 2018Inventors: Wen-Chia LIAO, Ying-Chen LIU, Chen-Ting CHIANG