Abstract: A light-emitting substrate includes a base substrate, an auxiliary electrode line, at least one light-emitting device, and at least one light-detecting device(s). The auxiliary electrode line is disposed on the base substrate. The at least one light-emitting device is disposed above the base substrate, and a light-emitting device includes a first electrode, a light-emitting functional layer and a second electrode that are sequentially stacked in a direction moving away from the base substrate. The at least one light-detecting device is disposed above the base substrate, and a light-detecting device includes a third electrode and a fourth electrode. The auxiliary electrode line is coupled to the fourth electrode and the second electrode.

Abstract: A display panel has a display region and a peripheral region. The display panel includes a substrate, a first metal layer disposed on the substrate, a planarization layer disposed on a side of the first metal layer away from the substrate, and a retaining wall structure located in the peripheral region and surrounding the display region. The first metal layer includes a signal line pattern located in the peripheral region. The planarization layer includes an opening in the peripheral region. At least a portion of the retaining wall structure is located in the opening. The signal line pattern is provided with at least one through hole, an orthogonal projection of the at least one through hole on the substrate is located within an orthogonal projection of the opening on the substrate, and is at least located on a side of an orthogonal projection of the retaining wall structure on the substrate.

Abstract: A ceiling fan blade assembly structure includes a blade holder, multiple fan blades, and multiple locking assemblies. Multiple fan blade assembly portions are disposed at an outer side of the blade holder. Each fan blade assembly portion includes two first side plates parallel to each other, a first radial positioning portion, and two first vertical positioning portions disposed on the two first side plates. Each fan blade has a fan blade connection portion that includes two second side plates, a second radial positioning portion, and two second vertical positioning portions. The second and the first radial positioning portions are engaged with each other, and the two second and first vertical positioning portions are engaged with each other. Accordingly, the fan blade connection portion is preliminarily positioned on the fan blade assembly portion. Through the locking assembly, the first and the second radial positioning portions are locked together.

Abstract: Embodiments of the present disclosure provide a method of fast optimization and compensation for volumetric positioning errors of rotary axes of a five-axis CNC system machine tool. The method comprises: establishing a volumetric positioning error model; forming an error database containing 12 geometrical error vectors; constructing a volumetric positioning error compensation table; establishing a compensation value optimization model; completing an iterative optimization of compensation values of volumetric positioning errors; generating a volumetric positioning error compensation file for a CNC system to complete compensation for the volumetric positioning errors; and updating the error database, detecting linkage trajectories of the rotary axes, and setting a linkage trajectory positioning error threshold, and guaranteeing accuracy by iteratively implementing detection, optimization, and compensation.

Abstract: A display panel has a display region, a fan-out region located on a side of the display region, and a bonding region located on a side of the fan-out region away from the display region. The display panel includes a gate driving circuit disposed in the display region, a plurality of data lines and a plurality of control signal lines that all extends from the display region to the fan-out region, and a plurality of data fan-out leads and a plurality of first fan-out leads that are all disposed in the fan-out region. Each data line is electrically connected to a data fan-out lead. The data fan-out leads are gathered to the bonding region. The control signal lines are electrically connected to the gate driving circuit. Each control signal line is electrically connected to a first fan-out lead. The first fan-out leads are gathered to the bonding region.

Abstract: A light guide plate structure includes a body and a plurality of microstructures. The body includes a first surface, a second surface, and a light incident surface. The light incident surface is connected to the first surface and the second surface. The light incident surface faces a light source, and light incident by the light source via the light incident surface has a light source direction on the body. The microstructures are formed on the first surface and have crests and troughs along a second direction, where projections of the crests on the first surface are distributed on a plurality of first wave trajectories, each of the first wave trajectories extends along the light source direction, and the troughs have ups and downs in the first direction. The light guide plate structure may improve the optical grade of pictures of a display device. A backlight module is also provided.

Abstract: A display panel includes: a substrate, sub-pixels and a gate drive circuit. The sub-pixel includes a pixel drive circuit. The gate drive circuit includes cascaded shift registers, and a shift register is electrically connected to pixel drive circuits in a row of sub-pixels. The gate drive circuit further includes cascade input signal lines and cascade display reset signal lines. The cascade input signal line is configured to connect a shift signal terminal and an input signal terminal of two different shift register; and the cascade display reset signal line is configured to connect a shift signal terminal and a display reset signal terminal of two different shift register. The display panel has sub-pixel regions for arranging the sub-pixels and first gap regions each located between two adjacent columns of sub-pixel regions; the cascade display reset signal lines and the cascade input signal lines are disposed in different first gap regions.

Abstract: A rotary bearing assembly is disclosed and includes an input shaft, an inner-ring component, an outer-ring component and a load element. The input shaft is configured to combine a rotating shaft of a motor to provide a power input. The inner-ring component includes a gear set, wherein the inner-ring component is sleeved on the input shaft through the gear set and driven by the input shaft. The outer-ring component is sleeved on the inner-ring component through a load element and engaged with the gear set, wherein when the gear set is driven by the input shaft to drive the inner-ring component, the gear set drives the outer-ring component, and the inner-ring component and the outer-ring component are rotated relatively, wherein one of the inner-ring component and the outer-ring component is served to provide a power output, and a rotational speed difference is between the power input and the power output.

Abstract: In one aspect, the present disclosure provides compounds which inhibit bromodomain testis (BRDT). In some embodiments, the compounds inhibit bromodomain-2 of BRDT. In another aspect, the present disclosure provides a method of inhibiting BRDT in a male subject, the method comprising administering to the male subject a therapeutically effective amount of a compound of the disclosure. In some embodiments, the method provides a contraceptive effect in the male subject.

Abstract: This application discloses a method for generating an image processing model performed by a computer device. The method includes: performing training by using a first source image sample, a first template image sample, and a first standard synthesized image, to obtain a first parameter adjustment model, and combining the first parameter adjustment model and a first resolution update layer into a first update model; adjusting the first update model into a second parameter adjustment model using a second source image sample and a second template image sample and a second standard synthesized image; combining the second parameter adjustment model and a second resolution update layer into a second update model; and adjusting the second update model into a target image fusion model using a third source image sample, a third template image sample and a third standard synthesized image.

Abstract: A method for compensating display of a spliced screen, including: obtaining a picture to be displayed; obtaining a theoretical brightness gain of at least one sub-display region in a plurality of sub-display regions; obtaining an actual brightness gain of the central region according to the theoretical brightness gain of at least part of the sub-display regions, and obtaining actual brightness gains of a plurality of first nodes in the non-central region according to the theoretical brightness gain of at least part of the sub-display regions; obtaining an actual brightness gain of at least part of the non-central region by using a bilinear interpolation method according to the actual brightness gains of the plurality of first nodes and an actual brightness gain of at least one second node on the central region; and compensating the picture to be displayed based on an actual brightness gain of the picture to be displayed.

Abstract: A display substrate includes: a base substrate, a plurality of pixel units and a plurality of initialization voltage signal lines. The pixel units are arranged in an array to form a plurality of rows of pixel units and a plurality of columns of pixel units, at least one pixel unit includes sub-pixels, and at least one sub-pixel includes a light-emitting element and a pixel driving circuit. The initialization voltage signal lines are configured to provide initialization voltage signals to the plurality of rows of pixel units respectively, and are arranged at intervals along a second direction. At least one initialization voltage signal line extends along a first direction. The plurality of rows of pixel units include a (2n?1)th row and a 2nth row and pixel driving circuits of the (2n?1)th row and pixel driving circuits of the 2nth rows share a common initialization voltage signal line.

Abstract: Described are embodiments of methods and systems for using a removable data storage device to efficiently transfer medical data from a medical device to a remote server. In some embodiments, the medical device tracks transfer statuses of medical data stored on a local storage. A transfer status assigned to a data portion of the medical data may inform the medical device of whether that data portion needs to be transferred, has been transferred, or has been successfully ingested at the remote server. The medical device can use information stored on the removable data storage device in conjunction with the tracked transfer statuses to determine which portions of the stored medical data should be transferred to a physically coupled removable data storage device. After completing a data transfer process, the medical device can update transfer statuses of portions of medical data that was transferred to the removable data storage device.

Abstract: A data management system comprises: a storage appliance configured to store a snapshot of a virtual machine; and one or more processors in communication with the storage appliance. The one or more processors are configured to perform operations including: identifying a plurality of shards of the virtual machine; requesting a snapshot of each of the plurality of shards; receiving the shards asynchronously; ordering the received snapshot shards sequentially into a results queue; and storing a single snapshot of the virtual machine based on the ordered snapshot shards. Operations may further include maintaining a flow control queue that limits the number of snapshot shards requested.

Abstract: The present disclosure describes a method for forming metallization layers that include a ruthenium metal liner and a cobalt metal fill. The method includes depositing a first dielectric on a substrate having a gate structure and source/drain (S/D) structures, forming an opening in the first dielectric to expose the S/D structures, and depositing a ruthenium metal on bottom and sidewall surfaces of the opening. The method further includes depositing a cobalt metal on the ruthenium metal to fill the opening, reflowing the cobalt metal, and planarizing the cobalt and ruthenium metals to form S/D conductive structures with a top surface coplanar with a top surface of the first dielectric.

Abstract: A multi-channel pipetting assembly includes a linkage member and a plurality of pipetting structures arranged in parallel. Each pipetting structure includes a pipette body, a piston rod, a piston tube, and an elastic element. The pipette body has a plurality of air chambers with different inner diameters, and the air chambers are arranged axially and communicate with each other. The piston rod is fixed to the linkage member. The piston tube is sleeved on the piston rod. The piston rod and the piston tube are located in the pipette body, and are axially and reciprocatingly movable in the pipette body. The piston rod matches the air chamber with the smallest inner diameter, and the piston tube matches the remaining air chambers. The elastic element is telescopically sleeved on the piston rod and corresponds to the piston tube. Therefore, a plurality of volume ranges meeting the accuracy requirements can be provided.

Abstract: A method for forming a Dynamic Random Access Memory (DRAM) includes forming an isolation structure in a substrate to define an active region. The method also includes forming a bit line trench in the active region to divide two active pillars. The method also includes forming a buried bit line in the bit line trench. The method also includes forming an insulating material over the bit line in the bit line trench. The top surface of the insulating material is lower than the top surface of the substrate. A trench is formed over the insulating material. The method also includes forming a shallow recess on the sidewalls of each of the active pillars exposed by the trench to make that each of the active pillars has a neck channel region. The method also includes forming a buried word line in the shallow recess.

Abstract: A manufacturing method of a package structure includes: forming a redistribution layer on a top surface of a glass substrate; forming a protective layer on the top surface of the glass substrate; cutting the glass substrate and the protective layer such that the glass substrate has a cutting edge, in which a crack is formed in the cutting edge of the glass substrate; and heating the protective layer such that a portion of the protective layer flows towards a bottom surface of the glass substrate to cover the cutting edge of the glass substrate and fill the crack in the cutting edge of the glass substrate.

Abstract: A semiconductor memory structure includes an isolation structure surrounding an active region in a substrate. The structure also includes two word lines disposed in the active region. The structure also includes a bit line contact disposed between two word lines. The structure also includes a first bit line disposed over the bit line contact. The bit line contact includes polysilicon and has a concave top surface.

Abstract: A package structure includes a substrate, a plurality of conductive pads, a light-emitting diode, a photo imageable dielectric material, and a black matrix. The substrate includes a top surface. The conductive pads are located on the top surface of the substrate. The light-emitting diode is located on the conductive pads. The photo imageable dielectric material is located between the light-emitting diode and the top surface of the substrate and between the conductive pads. An orthogonal projection of the light-emitting diode on the substrate is overlapped with an orthogonal projection of the photo imageable dielectric material on the substrate. The black matrix is located on the top surface of the substrate and the conductive pads.