Patents by Inventor Ying-Fu Tung
Ying-Fu Tung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11972972Abstract: A method for forming an isolation structure includes: forming a trench at a surface of a substrate; forming a mask pattern on the substrate, wherein the mask pattern has an opening communicated with the trench; filling a first isolation material layer in the opening and the trench, wherein a surface of the first isolation material layer defines a first recess; filling a second isolation material layer into the first recess; partially removing the first and second isolation material layers, to form a second recess, performing first and second oblique ion implantation processes, to form damage regions in the first isolation material layer; performing a decoupled plasma treatment, to transform portions of the damage regions into a protection layer having etching selectivity with respect to the damage regions; and removing the damage regions.Type: GrantFiled: October 12, 2021Date of Patent: April 30, 2024Assignee: Winbond Electronics Corp.Inventors: Che-Jui Hsu, Ying-Fu Tung, Chun-Sheng Lu, Mu-Lin Li
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Patent number: 11908953Abstract: A manufacturing method of a memory device are provided. The method includes following steps. A gate stacking structure is formed over a substrate. A first insulating layer, a second insulating layer and a mask material layer are sequentially formed over the substrate to cover the gate stacking structure. An ion implantation process is performed on the mask material layer to form a doped portion in the mask material layer. The doped portion caps on a top portion of the gate stacking structure. A first patterning process is performed on the mask material layer using the doped portion as a shadow mask to remove a bottom portion of the mask material layer extending along a surface of the substrate. A second patterning process is performed to remove the doped portion of the mask material layer and an exposed bottom portion of the second insulating layer surrounding the gate stacking structure.Type: GrantFiled: December 15, 2022Date of Patent: February 20, 2024Assignee: Winbond Electronics Corp.Inventors: Che-Jui Hsu, Ying-Fu Tung, Chun-Sheng Lu, Kuo-Feng Huang, Yu-Chi Kuo, Wang-Ta Li
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Publication number: 20230335602Abstract: A method of forming a semiconductor structure includes forming a mask layer on a substrate. The mask layer and the substrate include an opening. An isolation structure is formed in the opening. The mask layer is removed. A first conductive layer is formed on the isolation structure and the substrate. A first implantation process is performed on the first conductive layer and the isolation structure, to form a doped portion in the first conductive layer and a doped portion in the isolation structure. A second conductive layer is formed on the first conductive layer and the isolation structure. A first planarization process is performed, so that the top surfaces of the second conductive layer, the first conductive layer, and the isolation structure are aligned.Type: ApplicationFiled: April 18, 2022Publication date: October 19, 2023Inventors: Che-Jui HSU, Ying-Fu TUNG
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Patent number: 11637241Abstract: A RRAM and its manufacturing method are provided. The RRAM includes an interlayer dielectric layer, a first bottom contact structure, and a second bottom contact structure formed on a substrate. A first memory cell is formed on the first bottom contact structure. The first memory cell includes a first bottom electrode layer which includes a first conductive region. A pattern in which the first conductive region is vertically projected on the first bottom contact structure is a first projection pattern. A second memory cell is formed on the second bottom contact structure. The second memory cell includes a second bottom electrode layer which includes a second conductive region. A pattern in which the second conductive region is vertically projected on the second bottom contact structure is a second projection pattern. The second projection pattern is different from the first projection pattern.Type: GrantFiled: December 8, 2020Date of Patent: April 25, 2023Assignee: WINBOND ELECTRONICS CORP.Inventors: Meng-Hung Lin, Bo-Lun Wu, Po-Yen Hsu, Ying-Fu Tung, Han-Hsiu Chen
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Publication number: 20230121256Abstract: A manufacturing method of a memory device are provided. The method includes following steps. A gate stacking structure is formed over a substrate. A first insulating layer, a second insulating layer and a mask material layer are sequentially formed over the substrate to cover the gate stacking structure. An ion implantation process is performed on the mask material layer to form a doped portion in the mask material layer. The doped portion caps on a top portion of the gate stacking structure. A first patterning process is performed on the mask material layer using the doped portion as a shadow mask to remove a bottom portion of the mask material layer extending along a surface of the substrate. A second patterning process is performed to remove the doped portion of the mask material layer and an exposed bottom portion of the second insulating layer surrounding the gate stacking structure.Type: ApplicationFiled: December 15, 2022Publication date: April 20, 2023Applicant: Winbond Electronics Corp.Inventors: Che-Jui Hsu, Ying-Fu Tung, Chun-Sheng Lu, Kuo-Feng Huang, Yu-Chi Kuo, Wang-Ta Li
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Patent number: 11575051Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a gate stacking structure, a first insulating layer, a second insulating layer and a first spacer. The gate stacking structure is disposed over a substrate. The first insulating layer covers a top surface and a sidewall of the gate stacking structure. The second insulating layer covers a surface of the first insulating layer. A top corner region of the gate stacking structure is covered by the first and second insulating layers. The first spacer is located on the sidewall of the gate stacking structure, and covers a surface of the second insulating layer. A topmost end of the first spacer is lower than a topmost surface of the second insulating layer.Type: GrantFiled: August 20, 2020Date of Patent: February 7, 2023Assignee: Winbond Electronics Corp.Inventors: Che-Jui Hsu, Ying-Fu Tung, Chun-Sheng Lu, Kuo-Feng Huang, Yu-Chi Kuo, Wang-Ta Li
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Patent number: 11538818Abstract: A method of manufacturing a memory structure including the following steps is provided. A spacer layer is formed on sidewalls of gate stack structures. A protective material layer covering the spacer layer and the gate stack structures is formed. A mask material layer is formed on the protective material layer. There is a void located in the mask material layer between two adjacent gate stack structures. A first distance is between a top of the protective material layer and a top of the mask material layer. A second distance is between a top of the void and a top of the mask material layer above the void. A third distance is between a bottom of the void and a bottom of the mask material layer below the void. The first distance is greater than a sum of the second and third distances.Type: GrantFiled: July 21, 2021Date of Patent: December 27, 2022Assignee: Winbond Electronics Corp.Inventors: Che-Jui Hsu, Chun-Sheng Lu, Ying-Fu Tung, Chen-Wei Liao
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Publication number: 20220139764Abstract: A method for forming an isolation structure includes: forming a trench at a surface of a substrate; forming a mask pattern on the substrate, wherein the mask pattern has an opening communicated with the trench; filling a first isolation material layer in the opening and the trench, wherein a surface of the first isolation material layer defines a first recess; filling a second isolation material layer into the first recess; partially removing the first and second isolation material layers, to form a second recess, performing first and second oblique ion implantation processes, to form damage regions in the first isolation material layer; performing a decoupled plasma treatment, to transform portions of the damage regions into a protection layer having etching selectivity with respect to the damage regions; and removing the damage regions.Type: ApplicationFiled: October 12, 2021Publication date: May 5, 2022Applicant: Winbond Electronics Corp.Inventors: Che-Jui Hsu, Ying-Fu Tung, Chun-Sheng Lu, Mu-Lin Li
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Publication number: 20210351194Abstract: A method of manufacturing a memory structure including the following steps is provided. A spacer layer is formed on sidewalls of gate stack structures. A protective material layer covering the spacer layer and the gate stack structures is formed. A mask material layer is formed on the protective material layer. There is a void located in the mask material layer between two adjacent gate stack structures. A first distance is between a top of the protective material layer and a top of the mask material layer. A second distance is between a top of the void and a top of the mask material layer above the void. A third distance is between a bottom of the void and a bottom of the mask material layer below the void. The first distance is greater than a sum of the second and third distances.Type: ApplicationFiled: July 21, 2021Publication date: November 11, 2021Applicant: Winbond Electronics Corp.Inventors: Che-Jui Hsu, Chun-Sheng Lu, Ying-Fu Tung, Chen-Wei Liao
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Patent number: 11121142Abstract: A method of manufacturing a memory structure including the following steps is provided. A spacer layer is formed on sidewalls of gate stack structures. A protective material layer covering the spacer layer and the gate stack structures is formed. A mask material layer is formed on the protective material layer. There is a void located in the mask material layer between two adjacent gate stack structures. A first distance is between a top of the protective material layer and a top of the mask material layer. A second distance is between a top of the void and a top of the mask material layer above the void. A third distance is between a bottom of the void and a bottom of the mask material layer below the void. The first distance is greater than a sum of the second and third distances.Type: GrantFiled: December 31, 2019Date of Patent: September 14, 2021Assignee: Winbond Electronics Corp.Inventors: Che-Jui Hsu, Chun-Sheng Lu, Ying-Fu Tung, Chen-Wei Liao
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Patent number: 11101177Abstract: A method for forming a semiconductor structure includes: providing a substrate; forming a stacked structure on the substrate; forming a barrier layer on a sidewall of the stacked structure; forming a first dielectric layer covering the barrier layer and the stacked structure; removing a portion of the first dielectric layer to expose an upper portion of the stacked structure; forming a metal layer covering the stacked structure and the first dielectric layer; performing an annealing process to react the metal layer with the stacked structure to form a metal silicide layer at the upper portion of the stacked structure; removing an unreacted portion of the metal layer; removing a portion of the barrier layer to form a recess above the barrier layer; and forming a second dielectric layer covering the metal silicide layer and the first dielectric layer to form air gaps on both sides of the stacked structure.Type: GrantFiled: February 19, 2020Date of Patent: August 24, 2021Assignee: WINBOND ELECTRONICS CORP.Inventors: Che-Jui Hsu, Chun-Sheng Lu, Ying-Fu Tung, Mao-Chang Yen, Wan-Yu Peng
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Publication number: 20210257257Abstract: A method for forming a semiconductor structure includes: providing a substrate; forming a stacked structure on the substrate; forming a barrier layer on a sidewall of the stacked structure; forming a first dielectric layer covering the barrier layer and the stacked structure; removing a portion of the first dielectric layer to expose an upper portion of the stacked structure; forming a metal layer covering the stacked structure and the first dielectric layer; performing an annealing process to react the metal layer with the stacked structure to form a metal silicide layer at the upper portion of the stacked structure; removing an unreacted portion of the metal layer; removing a portion of the barrier layer to form a recess above the barrier layer; and forming a second dielectric layer covering the metal silicide layer and the first dielectric layer to form air gaps on both sides of the stacked structure.Type: ApplicationFiled: February 19, 2020Publication date: August 19, 2021Inventors: Che-Jui HSU, Chun-Sheng LU, Ying-Fu TUNG, Mao-Chang YEN, Wan-Yu PENG
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Publication number: 20210202512Abstract: A method of manufacturing a memory structure including the following steps is provided. A spacer layer is formed on sidewalls of gate stack structures. A protective material layer covering the spacer layer and the gate stack structures is formed. A mask material layer is formed on the protective material layer. There is a void located in the mask material layer between two adjacent gate stack structures. A first distance is between a top of the protective material layer and a top of the mask material layer. A second distance is between a top of the void and a top of the mask material layer above the void. A third distance is between a bottom of the void and a bottom of the mask material layer below the void. The first distance is greater than a sum of the second and third distances.Type: ApplicationFiled: December 31, 2019Publication date: July 1, 2021Applicant: Winbond Electronics Corp.Inventors: Che-Jui Hsu, Chun-Sheng Lu, Ying-Fu Tung, Chen-Wei Liao
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Publication number: 20210175421Abstract: A RRAM and its manufacturing method are provided. The RRAM includes an interlayer dielectric layer, a first bottom contact structure, and a second bottom contact structure formed on a substrate. A first memory cell is formed on the first bottom contact structure. The first memory cell includes a first bottom electrode layer which includes a first conductive region. A pattern in which the first conductive region is vertically projected on the first bottom contact structure is a first projection pattern. A second memory cell is formed on the second bottom contact structure. The second memory cell includes a second bottom electrode layer which includes a second conductive region. A pattern in which the second conductive region is vertically projected on the second bottom contact structure is a second projection pattern. The second projection pattern is different from the first projection pattern.Type: ApplicationFiled: December 8, 2020Publication date: June 10, 2021Inventors: Meng-Hung LIN, Bo-Lun WU, Po-Yen HSU, Ying-Fu TUNG, Han-Hsiu CHEN
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Publication number: 20210066493Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a gate stacking structure, a first insulating layer, a second insulating layer and a first spacer. The gate stacking structure is disposed over a substrate. The first insulating layer covers a top surface and a sidewall of the gate stacking structure. The second insulating layer covers a surface of the first insulating layer. A top corner region of the gate stacking structure is covered by the first and second insulating layers. The first spacer is located on the sidewall of the gate stacking structure, and covers a surface of the second insulating layer. A topmost end of the first spacer is lower than a topmost surface of the second insulating layer.Type: ApplicationFiled: August 20, 2020Publication date: March 4, 2021Applicant: Winbond Electronics Corp.Inventors: Che-Jui Hsu, Ying-Fu Tung, Chun-Sheng Lu, Kuo-Feng Huang, Yu-Chi Kuo, Wang-Ta Li