Abstract: A method includes forming a gate stack on a middle portion of s semiconductor fin, and forming a first gate spacer on a sidewall of the gate stack. After the first gate spacer is formed, a template dielectric region is formed to cover the semiconductor fin. The method further includes recessing the template dielectric region. After the recessing, a second gate spacer is formed on the sidewall of the gate stack. The end portion of the semiconductor fin is etched to form a recess in the template dielectric region. A source/drain region is epitaxially grown in the recess.

Abstract: A semiconductor structure includes a substrate, a fin, a bottom capping structure and a top capping structure. The fin disposed on the substrate, the fin has a lower portion and an upper portion extending upwards from the lower portion. The bottom capping structure covers a sidewall of the lower portion of the fin. The top capping structure covers a sidewall of the upper portion of the fin.

Abstract: A multi-gate semiconductor device is formed that provides a first fin element extending from a substrate. A gate structure extends over a channel region of the first fin element. The channel region of the first fin element includes a plurality of channel semiconductor layers each surrounded by a portion of the gate structure. A source/drain region of the first fin element is adjacent the gate structure. The source/drain region includes a first semiconductor layer, a dielectric layer over the first semiconductor layer, and a second semiconductor layer over the dielectric layer.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin structure on a substrate; a first gate stack and a second gate stack formed on the fin structure; a dielectric material layer disposed on the first and second gate stacks, wherein the dielectric layer includes a first portion disposed on a sidewall of the first gate stack with a first thickness and a second portion disposed on a sidewall of the second gate stack with a second thickness greater than the first thickness; a first gate spacer disposed on the first portion of the dielectric material layer; and a second gate spacer disposed on the second portion of the dielectric material layer.

Abstract: A method for fabricating a semiconductor device having a substantially undoped channel region includes forming a plurality of fins extending from a substrate. In various embodiments, each of the plurality of fins includes a portion of a substrate, a portion of a first epitaxial layer on the portion of the substrate, and a portion of a second epitaxial layer on the portion of the first epitaxial layer. The portion of the first epitaxial layer of each of the plurality of fins is oxidized, and a liner layer is formed over each of the plurality of fins. Recessed isolation regions are then formed adjacent to the liner layer. The liner layer may then be etched to expose a residual material portion (e.g., Ge residue) adjacent to a bottom surface of the portion of the second epitaxial layer of each of the plurality of fins, and the residual material portion is removed.

Abstract: The present disclosure provides a method, which includes forming a first fin structure and a second fin structure over a substrate, which has a first trench positioned between the first and second fin structures. The method also includes forming a first dielectric layer within the first trench, recessing the first dielectric layer to expose a portion of the first fin structure, forming a first capping layer over the exposed portion of the first fin structure and the recessed first dielectric layer in the first trench, forming a second dielectric layer over the first capping layer in the first trench while the first capping layer covers the exposed portion of the first fin feature and removing the first capping layer from the first fin structure.

Abstract: Devices and structures that include a gate spacer having a gap or void are described along with methods of forming such devices and structures. In accordance with some embodiments, a structure includes a substrate, a gate stack over the substrate, a contact over the substrate, and a spacer disposed laterally between the gate stack and the contact. The spacer includes a first dielectric sidewall portion and a second dielectric sidewall portion. A void is disposed between the first dielectric sidewall portion and the second dielectric sidewall portion.

Abstract: A multi-gate semiconductor device having a fin element, a gate structure over the fin element, an epitaxial source/drain feature adjacent the fin element; a dielectric spacer interposing the gate structure and the epitaxial source/drain feature.

Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.

Abstract: A device includes a first semiconductor strip, a first gate dielectric encircling the first semiconductor strip, a second semiconductor strip overlapping the first semiconductor strip, and a second gate dielectric encircling the second semiconductor strip. The first gate dielectric contacts the first gate dielectric. A gate electrode has a portion over the second semiconductor strip, and additional portions on opposite sides of the first and the second semiconductor strips and the first and the second gate dielectrics.

Abstract: A method for fabricating a semiconductor device having a substantially undoped channel region includes forming a plurality of fins extending from a substrate. In various embodiments, each of the plurality of fins includes a portion of a substrate, a portion of a first epitaxial layer on the portion of the substrate, and a portion of a second epitaxial layer on the portion of the first epitaxial layer. The portion of the first epitaxial layer of each of the plurality of fins is oxidized, and a liner layer is formed over each of the plurality of fins. Recessed isolation regions are then formed adjacent to the liner layer. The liner layer may then be etched to expose a residual material portion (e.g., Ge residue) adjacent to a bottom surface of the portion of the second epitaxial layer of each of the plurality of fins, and the residual material portion is removed.

Abstract: The present disclosure provides a method, which includes forming a first fin structure and a second fin structure over a substrate, which has a first trench positioned between the first and second fin structures. The method also includes forming a first dielectric layer within the first trench, recessing the first dielectric layer to expose a portion of the first fin structure, forming a first capping layer over the exposed portion of the first fin structure and the recessed first dielectric layer in the first trench, forming a second dielectric layer over the first capping layer in the first trench while the first capping layer covers the exposed portion of the first fin feature and removing the first capping layer from the first fin structure.

Abstract: A method of semiconductor device fabrication is described that includes forming a fin extending from a substrate and having a source/drain region and a channel region. The fin includes a first epitaxial layer having a first composition and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having a second composition. The second epitaxial layer is removed from the source/drain region of the fin to form a gap. The gap is filled with a dielectric material. Another epitaxial material is formed on at least two surfaces of the first epitaxial layer to form a source/drain feature.

Abstract: The present disclosure provides a fin-like field effect transistor (FinFET) device and a method of fabrication thereof. The method includes forming a fin on a substrate and forming a gate structure wrapping the fin. A pair of spacers is formed adjacent to the gate structure and the gate structure is removed. Afterwards, a pair of oxide layers is deposited adjacent to the pair of spacers. A pair of gate dielectric layers is deposited next to the pair of oxide layers. Finally, a metal gate is formed between the pair of gate dielectric layers.

Abstract: Devices and structures that include a gate spacer having a gap or void are described along with methods of forming such devices and structures. In accordance with some embodiments, a structure includes a substrate, a gate stack over the substrate, a contact over the substrate, and a spacer disposed laterally between the gate stack and the contact. The spacer includes a first dielectric sidewall portion and a second dielectric sidewall portion. A void is disposed between the first dielectric sidewall portion and the second dielectric sidewall portion.

Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.

Abstract: A device includes isolation regions extending into a semiconductor substrate, with a substrate strip between opposite portions of the isolation regions having a first width. A source/drain region has a portion overlapping the substrate strip, wherein an upper portion of the source/drain region has a second width greater than the first width. The upper portion of the source/drain region has substantially vertical sidewalls. A source/drain silicide region has inner sidewalls contacting the vertical sidewalls of the source/drain region.

Abstract: A semiconductor layer is etched into a plurality of fin structures. A first nitridation process is performed to side surfaces of the fin structures. The first nitridation process forms a first oxynitride layer at the side surfaces of the fin structures. A liner oxide layer is formed on the first oxynitride layer. An isolation structure is formed around the fin structures after the forming of the liner oxide layer.

Abstract: A semiconductor device includes a substrate including a first fin element, a second fin element, and a third fin element. A first source/drain epitaxial feature is disposed over the first and second fin elements. A first portion of the first source/drain epitaxial feature disposed on the first fin element and a second portion of the first source/drain epitaxial feature disposed on the second fin element merge at a merge point. A second source/drain epitaxial feature is disposed over the third fin element. A first sidewall of the second source/drain epitaxial feature interfaces a first third-fin spacer disposed along a first sidewall of the third fin element. A second sidewall of the second source/drain epitaxial feature interfaces a second third-fin spacer disposed along a second sidewall of the third fin element. The merge point has a first height less than a second height of the first third-fin spacer.

Abstract: A semiconductor layer is etched into a plurality of fin structures. A first nitridation process is performed to side surfaces of the fin structures. The first nitridation process forms a first oxynitride layer at the side surfaces of the fin structures. A liner oxide layer is formed on the first oxynitride layer. An isolation structure is formed around the fin structures after the forming of the liner oxide layer.