Patents by Inventor Ying-Lang Wang
Ying-Lang Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11955553Abstract: Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.Type: GrantFiled: February 24, 2023Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Su-Hao Liu, Kuo-Ju Chen, Wen-Yen Chen, Ying-Lang Wang, Liang-Yin Chen, Li-Ting Wang, Huicheng Chang
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Publication number: 20240088225Abstract: A method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. At least a portion of the semiconductor region is molten during the melt anneal.Type: ApplicationFiled: November 14, 2023Publication date: March 14, 2024Inventors: Su-Hao Liu, Wen-Yen Chen, Li-Heng Chen, Li-Ting Wang, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo, Ying-Lang Wang
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Patent number: 11855146Abstract: A method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. At least a portion of the semiconductor region is molten during the melt anneal.Type: GrantFiled: January 17, 2022Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Su-Hao Liu, Wen-Yen Chen, Li-Heng Chen, Li-Ting Wang, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo, Ying-Lang Wang
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Publication number: 20230360919Abstract: A method of thinning a wafer includes measuring an initial thickness of the wafer. The method further includes calculating a polishing time using the initial thickness. The method further includes polishing the wafer for a first duration equal to the polishing time to obtain a polished wafer. The method further includes measuring a polished thickness of the polished wafer. The method further includes calculating an etching time using the polished thickness. The method further includes etching the polished wafer for a second duration equal to the etching time to obtain an etched wafer, wherein the wafer has a total thickness variation of less than or equal to 0.15 ?m after etching the polished wafer.Type: ApplicationFiled: July 21, 2023Publication date: November 9, 2023Inventors: Yuan-Hsuan CHEN, Kei-Wei CHEN, Ying-Lang WANG, Kuo-Hsiu WEI
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Publication number: 20230317519Abstract: The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.Type: ApplicationFiled: June 7, 2023Publication date: October 5, 2023Inventors: Li-Chieh Wu, Tang-Kuei Chang, Kuo-Hsiu Wei, Kei-Wei Chen, Ying-Lang Wang, Su-Hao Liu, Kuo-Ju Chen, Liang-Yin Chen, Huicheng Chang, Ting-Kui Chang, Chia Hsuan Lee
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Patent number: 11728172Abstract: An apparatus includes a first metrology tool configured to measure an initial thickness of a wafer. The apparatus includes a controller connected to the first metrology tool and configured to calculate a polishing time based on a material removal rate, a predetermined thickness and the initial thickness of the wafer. The apparatus includes a polishing tool connected to the controller and configured to polish the wafer for a first duration equal to the polishing time. The apparatus includes a second metrology tool connected to the controller and configured to measure a polished thickness. The controller is configured for receiving the initial thickness from the first metrology tool and the polished thickness from the second metrology tool, updating the material removal rate based on the predetermined thickness, the polishing time and the polished thickness, and calculating an etching time for etching the polished wafer using the polished thickness.Type: GrantFiled: April 30, 2020Date of Patent: August 15, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yuan-Hsuan Chen, Kei-Wei Chen, Ying-Lang Wang, Kuo-Hsiu Wei
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Patent number: 11710659Abstract: The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.Type: GrantFiled: December 27, 2021Date of Patent: July 25, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Li-Chieh Wu, Tang-Kuei Chang, Kuo-Hsiu Wei, Kei-Wei Chen, Ying-Lang Wang, Su-Hao Liu, Kuo-Ju Chen, Liang-Yin Chen, Huicheng Chang, Ting-Kui Chang, Chia Hsuan Lee
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Patent number: 11685013Abstract: A polishing pad includes a pad layer and one or more polishing structures over an upper surface of the pad layer, where each of the one or more polishing structures has a pre-determined shape and is formed at a pre-determined location of the pad layer, where the one or more polishing structures comprise at least one continuous line shaped segment extending along the upper surface of the pad layer, where each of the one or more polishing structures is a homogeneous material.Type: GrantFiled: July 2, 2018Date of Patent: June 27, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih Hung Chen, Kei-Wei Chen, Ying-Lang Wang
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Publication number: 20230197852Abstract: Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.Type: ApplicationFiled: February 24, 2023Publication date: June 22, 2023Inventors: Su-Hao Liu, Kuo-Ju Chen, Wen-Yen Chen, Ying-Lang Wang, Liang-Yin Chen, Li-Ting Wang, Huicheng Chang
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Publication number: 20230154985Abstract: A method of forming a semiconductor structure includes following operations. A substrate including a silicon (Si) layer is received. An amorphous germanium (Ge) layer is formed on the Si layer. A barrier layer is formed over the amorphous Ge layer. The substrate is annealed to transform the Si layer and the Ge layer to form a single crystalline SiGe layer. A Ge concentration is in a positive correlation with a ratio of a thickness of the Ge layer and a thickness of the Si layer.Type: ApplicationFiled: January 13, 2022Publication date: May 18, 2023Inventors: TE-MING KUNG, YING-LANG WANG, KEI-WEI CHEN, WEN-HSI LEE, SHU WEI CHANG
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Patent number: 11631618Abstract: Various embodiments provide a thickness sensor and method for measuring a thickness of discrete conductive features, such as conductive lines and plugs. In one embodiment, the thickness sensor generates an Eddy current in a plurality of discrete conductive features, and measures the generated Eddy current generated in the discrete conductive features. The thickness sensor has a small sensor spot size, and amplifies peaks and valleys of the measured Eddy current. The thickness sensor determines a thickness of the discrete conductive features based on a difference between a minimum amplitude value and a maximum amplitude value of the measured Eddy current.Type: GrantFiled: January 6, 2021Date of Patent: April 18, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih Hung Chen, Kei-Wei Chen, Ying-Lang Wang
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Patent number: 11621342Abstract: In an embodiment, a method includes: performing a self-limiting process to modify a top surface of a wafer; after the self-limiting process completes, removing the modified top surface from the wafer; and repeating the performing the self-limiting process and the removing the modified top surface from the wafer until a thickness of the wafer is decreased to a predetermined thickness.Type: GrantFiled: October 12, 2020Date of Patent: April 4, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih Hung Chen, Kei-Wei Chen, Ying-Lang Wang
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Patent number: 11594636Abstract: Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.Type: GrantFiled: February 17, 2022Date of Patent: February 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Su-Hao Liu, Kuo-Ju Chen, Wen-Yen Chen, Ying-Lang Wang, Liang-Yin Chen, Li-Ting Wang, Huicheng Chang
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Publication number: 20220173239Abstract: Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.Type: ApplicationFiled: February 17, 2022Publication date: June 2, 2022Inventors: Su-Hao Liu, Kuo-Ju Chen, Wen-Yen Chen, Ying-Lang Wang, Liang-Yin Chen, Li-Ting Wang, Huicheng Chang
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Patent number: 11329221Abstract: The present disclosure, in some embodiments, relates to a method of forming a resistive random access memory (RRAM) device. The method includes forming one or more bottom electrode films over a lower interconnect layer within a lower inter-level dielectric layer. A data storage film having a variable resistance is formed above the one or more bottom electrode films. A lower top electrode film including a metal is over the data storage film, one or more oxygen barrier films are over the lower top electrode film, and an upper top electrode film including a metal nitride is formed over the one or more oxygen barrier films. The one or more oxygen barrier films include one or more of a metal oxide film and a metal oxynitride film. The upper top electrode film is formed to be completely confined over a top surface of the one or more oxygen barrier films.Type: GrantFiled: November 25, 2019Date of Patent: May 10, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Ting Chu, Tong-Chern Ong, Ying-Lang Wang
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Publication number: 20220140079Abstract: A method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. At least a portion of the semiconductor region is molten during the melt anneal.Type: ApplicationFiled: January 17, 2022Publication date: May 5, 2022Inventors: Su-Hao Liu, Wen-Yen Chen, Li-Heng Chen, Li-Ting Wang, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo, Ying-Lang Wang
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Publication number: 20220122884Abstract: The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.Type: ApplicationFiled: December 27, 2021Publication date: April 21, 2022Inventors: Li-Chieh Wu, Tang-Kuei Chang, Kuo-Hsiu Wei, Kei-Wei Chen, Ying-Lang Wang, Su-Hao Liu, Kuo-Ju Chen, Liang-Yin Chen, Huicheng Chang, Ting-Kui Chang, Chia Hsuan Lee
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Patent number: 11257952Abstract: Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.Type: GrantFiled: May 18, 2020Date of Patent: February 22, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Su-Hao Liu, Kuo-Ju Chen, Wen-Yen Chen, Ying-Lang Wang, Liang-Yin Chen, Li-Ting Wang, Huicheng Chang
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Patent number: 11227918Abstract: A method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. At least a portion of the semiconductor region is molten during the melt anneal.Type: GrantFiled: May 24, 2019Date of Patent: January 18, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Su-Hao Liu, Wen-Yen Chen, Li-Heng Chen, Li-Ting Wang, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo, Ying-Lang Wang
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Patent number: 11211289Abstract: The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.Type: GrantFiled: August 30, 2019Date of Patent: December 28, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Chieh Wu, Tang-Kuei Chang, Kuo-Hsiu Wei, Kei-Wei Chen, Ying-Lang Wang, Su-Hao Liu, Kuo-Ju Chen, Liang-Yin Chen, Huicheng Chang, Ting-Kui Chang, Chia Hsuan Lee