Patents by Inventor Ying-Tso Chen
Ying-Tso Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9312139Abstract: A semiconductor element and a manufacturing method of the same are provided. The semiconductor element includes a substrate, a plurality of doping strips, a memory material layer, a plurality of conductive damascene structures, and a dielectric structure. The doping strips are formed in the substrate. The memory material layer is formed on the substrate, and the memory material layer comprises a memory area located on two sides of the doping strips. The conductive damascene structures are formed on the memory material layer. The dielectric structure is formed on the doping strips and between the conductive damascene structures. The conductive damascene structures are extended in a direction perpendicular to a direction which the doping strips are extended in.Type: GrantFiled: May 10, 2013Date of Patent: April 12, 2016Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Ching-Hung Wang, Jyun-Siang Huang, Chien-Hung Liu, Chia-Wen Cheng, Ying-Tso Chen
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Patent number: 8969202Abstract: A method of manufacturing a metal silicide is disclosed below. A substrate having a first region and a second region is provided. A silicon layer is formed on the substrate. A planarization process is performed to make the silicon layer having a planar surface. A part of the silicon layer is removed to form a plurality of first gates on the first region and to form a plurality of second gates on the second region. The height of the first gates is greater than the height of the second gates, and top surfaces of the first gates and the second gates have the same height level. A dielectric layer covering the first gates and the second gates is formed and exposes the top surfaces of the first gates and the second gates. A metal silicide is formed on the top surfaces of the first gates and the second gates.Type: GrantFiled: February 7, 2014Date of Patent: March 3, 2015Assignee: Macronix International Co., Ltd.Inventors: Yen-Hao Shih, Ying-Tso Chen, Shih-Chang Tsai, Chun-Fu Chen
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Publication number: 20140264545Abstract: A semiconductor element and a manufacturing method of the same are provided. The semiconductor element includes a substrate, a plurality of doping strips, a memory material layer, a plurality of conductive damascene structures, and a dielectric structure. The doping strips are formed in the substrate. The memory material layer is formed on the substrate, and the memory material layer comprises a memory area located on two sides of the doping strips. The conductive damascene structures are formed on the memory material layer. The dielectric structure is formed on the doping strips and between the conductive damascene structures. The conductive damascene structures are extended in a direction perpendicular to a direction which the doping strips are extended in.Type: ApplicationFiled: May 10, 2013Publication date: September 18, 2014Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Ching-Hung Wang, Jyun-Siang Huang, Chien-Hung Liu, Chia-Wen Cheng, Ying-Tso Chen
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Patent number: 8809933Abstract: A semiconductor device including a substrate, a plurality of stacked gate structures, a plurality of doped regions, a plurality of liner layers, a plurality of conductive layers, a plurality of dielectric layers and a plurality of word lines is provided. The substrate has a plurality of trenches therein. The stacked gate structures are on the substrate between the trenches. The doped regions are in the substrate at sidewalls or bottoms of the trenches. The liner layers are on at least a portion of sidewalls of the stacked gate structures and on sidewalls of the trenches. The conductive layers are in the trenches and electrically connected to the doped regions. The dielectric layers are on the conductive layers and between the stacked gate structures. The word lines are on the substrate and electrically connected to the stacked gate structures.Type: GrantFiled: July 12, 2010Date of Patent: August 19, 2014Assignee: MACRONIX International Co., Ltd.Inventors: Guan-De Lee, Chien-Hung Liu, Shou-Wei Huang, Ying-Tso Chen
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Publication number: 20140154881Abstract: A method of manufacturing a metal silicide is disclosed below. A substrate having a first region and a second region is provided. A silicon layer is formed on the substrate. A planarization process is performed to make the silicon layer having a planar surface. A part of the silicon layer is removed to form a plurality of first gates on the first region and to form a plurality of second gates on the second region. The height of the first gates is greater than the height of the second gates, and top surfaces of the first gates and the second gates have the same height level. A dielectric layer covering the first gates and the second gates is formed and exposes the top surfaces of the first gates and the second gates. A metal silicide is formed on the top surfaces of the first gates and the second gates.Type: ApplicationFiled: February 7, 2014Publication date: June 5, 2014Applicant: Macronix International Co., Ltd.Inventors: Yen-Hao Shih, Ying-Tso Chen, Shih-Chang Tsai, Chun-Fu Chen
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Patent number: 8674410Abstract: A method of manufacturing a metal silicide is disclosed below. A substrate having a first region and a second region is proviced. A silicon layer is formed on the substrate. A planarization process is performed to make the silicon layer having a planar surface. A part of the silicon layer is removed to form a plurality of first gates on the first region and to form a plurality of second gates on the second region. The height of the first gates is greater than the height of the second gates, and top surfaces of the first gates and the second gates have the same height level. A dielectric layer covering the first gates and the second gates is formed and exposes the top surfaces of the first gates and the second gates. A metal silicide is formed on the top surfaces of the first gates and the second gates.Type: GrantFiled: March 7, 2012Date of Patent: March 18, 2014Assignee: Macronix International Co., Ltd.Inventors: Yen-Hao Shih, Ying-Tso Chen, Shih-Chang Tsai, Chun-Fu Chen
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Publication number: 20130234210Abstract: A method of manufacturing a metal silicide is disclosed below. A substrate having a first region and a second region is proviced. A silicon layer is formed on the substrate. A planarization process is performed to make the silicon layer having a planar surface. A part of the silicon layer is removed to form a plurality of first gates on the first region and to form a plurality of second gates on the second region. The height of the first gates is greater than the height of the second gates, and top surfaces of the first gates and the second gates have the same height level. A dielectric layer covering the first gates and the second gates is formed and exposes the top surfaces of the first gates and the second gates. A metal silicide is formed on the top surfaces of the first gates and the second gates.Type: ApplicationFiled: March 7, 2012Publication date: September 12, 2013Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Yen-Hao Shih, Ying-Tso Chen, Shih-Chang Tsai, Chun-Fu Chen
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Patent number: 8084779Abstract: A casting adapted to carry a light emitting diode die and an anti-static die is disclosed. The casting comprises two electrodes for opposite electrodes and a wall. The light emitting diode die is mounted one of electrodes and the anti-static die is mounted on the other electrode. The wall is arranged between the light emitting diode die and the anti-static die. Further, the height of the wall is larger than that of the anti-static die to shade the anti-static die, whereby reflecting the light emitted from the light emitting diode die. Therefore, the reflection ratio of the light emitting diode die is improved, and the intensity generated by the whole light emitting diode is also improved.Type: GrantFiled: February 9, 2010Date of Patent: December 27, 2011Assignee: Lextar Electronics Corp.Inventors: Ying-Tso Chen, Teng-Huei Huang
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Publication number: 20110198698Abstract: A semiconductor device including a substrate, a plurality of stacked gate structures, a plurality of doped regions, a plurality of liner layers, a plurality of conductive layers, a plurality of dielectric layers and a plurality of word lines is provided. The substrate has a plurality of trenches therein. The stacked gate structures are on the substrate between the trenches. The doped regions are in the substrate at sidewalls or bottoms of the trenches. The liner layers are on at least a portion of sidewalls of the stacked gate structures and on sidewalls of the trenches. The conductive layers are in the trenches and electrically connected to the doped regions. The dielectric layers are on the conductive layers and between the stacked gate structures. The word lines are on the substrate and electrically connected to the stacked gate structures.Type: ApplicationFiled: July 12, 2010Publication date: August 18, 2011Applicant: MACRONIX International Co., Ltd.Inventors: GUAN-DE LEE, Chien-Hung Liu, Shou-Wei Huang, Ying-Tso Chen
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Patent number: 7804122Abstract: A non-volatile memory includes a substrate having two openings, a stacked gate structure disposed on the substrate between the two openings, a liner disposed on a bottom of each of the two openings and parts of a sidewall of each of the two openings, a second conductive layer disposed on the liner at the bottom of each of the two openings, and a third conductive layer on the second conductive layer and the liner. The stacked gate structure includes a first dielectric layer, a charge storage layer, a second dielectric layer, and a first conductive layer. The liner has a top surface lower than that of the substrate. The second conductive layer has a top surface co-planar with that of the liner. The third conductive layer has a top surface at least co-planar with that of the substrate and lower than that of the first dielectric layer.Type: GrantFiled: May 4, 2009Date of Patent: September 28, 2010Assignee: MACRONIX International Co., LtdInventors: Chin-Hsien Chen, Ying-Tso Chen, Chien-Hung Liu, Shou-Wei Huang
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Publication number: 20100133576Abstract: A casting adapted to carry a light emitting diode die and an anti-static die is disclosed. The casting comprises two electrodes for opposite electrodes and a wall. The light emitting diode die is mounted one of electrodes and the anti-static die is mounted on the other electrode. The wall is arranged between the light emitting diode die and the anti-static die. Further, the height of the wall is larger than that of the anti-static die to shade the anti-static die, whereby reflecting the light emitted from the light emitting diode die. Therefore, the reflection ratio of the light emitting diode die is improved, and the intensity generated by the whole light emitting diode is also improved.Type: ApplicationFiled: February 9, 2010Publication date: June 3, 2010Applicant: LIGHTHOUSE TECHNOLOGY CO., LTD.Inventors: Ying-Tso Chen, Teng-Huei Huang
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Patent number: 7714347Abstract: A casting adapted to carry a light emitting diode die and an anti-static die is disclosed. The casting comprises two electrodes for opposite electrodes and a wall. The light emitting diode die is mounted one of electrodes and the anti-static die is mounted on the other electrode. The wall is arranged between the light emitting diode die and the anti-static die. Further, the height of the wall is larger than that of the anti-static die to shade the anti-static die, whereby reflecting the light emitted from the light emitting diode die. Therefore, the reflection ratio of the light emitting diode die is improved, and the intensity generated by the whole light emitting diode is also improved.Type: GrantFiled: September 12, 2006Date of Patent: May 11, 2010Assignee: Lighthouse Technology Co., Ltd.Inventors: Ying-Tso Chen, Teng-Huei Huang
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Patent number: 7608504Abstract: A memory is provided. The memory includes a substrate, a number of parallel bit lines, a number of parallel word lines and at least a oxide-nitride-oxide (ONO) structure. The bit lines are disposed in the substrate. The word lines are disposed on the substrate. The word lines are crossed with but not perpendicular to the bit lines. The ONO structure is disposed between the word lines and the substrate.Type: GrantFiled: August 30, 2006Date of Patent: October 27, 2009Assignee: Macronix International Co., Ltd.Inventors: Chien-Hung Liu, Shou-Wei Huang, Ying-Tso Chen, Yu-Tsung Lin
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Publication number: 20090212353Abstract: A non-volatile memory includes a substrate having two openings, a stacked gate structure disposed on the substrate between the two openings, a liner disposed on a bottom of each of the two openings and parts of a sidewall of each of the two openings, a second conductive layer disposed on the liner at the bottom of each of the two openings, and a third conductive layer on the second conductive layer and the liner. The stacked gate structure includes a first dielectric layer, a charge storage layer, a second dielectric layer, and a first conductive layer. The liner has a top surface lower than that of the substrate. The second conductive layer has a top surface co-planar with that of the liner. The third conductive layer has a top surface at least co-planar with that of the substrate and lower than that of the first dielectric layer.Type: ApplicationFiled: May 4, 2009Publication date: August 27, 2009Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chin-Hsien Chen, Ying-Tso Chen, Chien-Hung Liu, Shou-Wei Huang
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Patent number: 7572691Abstract: A method of fabricating a non-volatile memory is provided. First, two openings are formed on a substrate. A stacked gate structure comprising a first dielectric layer, a charge storage layer, a second dielectric layer and a first conductive layer is formed on the substrate between the two openings. A liner is formed on a bottom and a portion of a sidewall of the tow openings, wherein a top surface of the liner is lower than that of the substrate. A second conductive layer is formed on the liner at the bottom of the two openings, wherein a top surface of the second conductive layer is co-planar with that of the liner. A third conductive layer is formed on the second conductive layer and the liner, wherein a top surface of the third conductive layer is co-planar with that of the substrate and lower than that of the first dielectric layer.Type: GrantFiled: May 16, 2006Date of Patent: August 11, 2009Assignee: MACRONIX International Co., LtdInventors: Chin-Hsien Chen, Ying-Tso Chen, Chien-Hung Liu, Shou-Wei Huang
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Publication number: 20080054322Abstract: A memory is provided. The memory includes a substrate, a number of parallel bit lines, a number of parallel word lines and at least a oxide-nitride-oxide (ONO) structure. The bit lines are disposed in the substrate. The word lines are disposed on the substrate. The word lines are crossed with but not perpendicular to the bit lines. The ONO structure is disposed between the word lines and the substrate.Type: ApplicationFiled: August 30, 2006Publication date: March 6, 2008Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chien-Hung Liu, Shou-Wei Huang, Ying-Tso Chen, Yu-Tsung Lin
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Publication number: 20080048346Abstract: A method of forming a conductive line suitable for decreasing a sheet resistance of the conductive lines. The method comprises steps of providing a material layer having a conductive layer formed thereon and forming a patterned mask layer on the conductive layer. In addition, a portion of the conductive layer is removed by using the patterned mask layer as a mask and a spacer is formed on a sidewall of the patterned mask layer and the conductive layer. A portion of the conductive layer is removed until the material layer is exposed to form a conductive line, wherein the spacer and the patterned mask layer serve as a mask.Type: ApplicationFiled: October 30, 2007Publication date: February 28, 2008Inventors: JUI-PIN CHANG, CHIEN-HUNG LIU, YING-TSO CHEN, SHOU-WEI HUANG
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Publication number: 20070284605Abstract: A casting adapted to carry a light emitting diode die and an anti-static die is disclosed. The casting comprises two electrodes for opposite electrodes and a wall. The light emitting diode die is mounted one of electrodes and the anti-static die is mounted on the other electrode. The wall is arranged between the light emitting diode die and the anti-static die. Further, the height of the wall is larger than that of the anti-static die to shade the anti-static die, whereby reflecting the light emitted from the light emitting diode die. Therefore, the reflection ratio of the light emitting diode die is improved, and the intensity generated by the whole light emitting diode is also improved.Type: ApplicationFiled: September 12, 2006Publication date: December 13, 2007Inventors: Ying-Tso Chen, Teng-Huei Huang
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Patent number: 7307018Abstract: A method of forming a conductive line suitable for decreasing a sheet resistance of the conductive lines. The method comprises steps of providing a material layer having a conductive layer formed thereon and forming a patterned mask layer on the conductive layer. In addition, a portion of the conductive layer is removed by using the patterned mask layer as a mask and a spacer is formed on a sidewall of the patterned mask layer and the conductive layer. A portion of the conductive layer is removed until the material layer is exposed to form a conductive line, wherein the spacer and the patterned mask layer serve as a mask.Type: GrantFiled: September 27, 2005Date of Patent: December 11, 2007Assignee: Macronix International Co., Ltd.Inventors: Jui-Pin Chang, Chien-Hung Liu, Ying-Tso Chen, Shou-Wei Huang
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Publication number: 20070269943Abstract: A method of fabricating a non-volatile memory is provided. First, two openings are formed on a substrate. A stacked gate structure comprising a first dielectric layer, a charge storage layer, a second dielectric layer and a first conductive layer is formed on the substrate between the two openings. A liner is formed on a bottom and a portion of a sidewall of the tow openings, wherein a top surface of the liner is lower than that of the substrate. A second conductive layer is formed on the liner at the bottom of the two openings, wherein a top surface of the second conductive layer is co-planar with that of the liner. A third conductive layer is formed on the second conductive layer and the liner, wherein a top surface of the third conductive layer is co-planar with that of the substrate and lower than that of the first dielectric layer.Type: ApplicationFiled: May 16, 2006Publication date: November 22, 2007Inventors: Chin-Hsien Chen, Ying-Tso Chen, Chien-Hung Liu, Shou-Wei Huang