Abstract: A memory cell that includes a control gate disposed laterally between two floating gates where each floating gate is capable of holding data. Each floating gate in a memory cell may be erased and programmed by applying a combination of voltages to diffusion regions, the control gate, and a well. A plurality of memory cells creates a memory string, and a memory array is formed from a plurality of memory strings arranged in rows and columns.

Abstract: A memory cell that includes a control gate disposed laterally between two floating gates where each floating gate is capable of holding data. Each floating gate in a memory cell may be erased and programmed by applying a combination of voltages to diffusion regions, the control gate, and a well. A plurality of memory cells creates a memory string, and a memory array is formed from a plurality of memory strings arranged in rows and columns.

Abstract: A self-aligned method for manufacturing an electrically alterable memory device on a semiconductor layer includes (a) forming an insulating layer on the semiconductor layer, (b) depositing a first conductive layer on the insulating layer, (c) forming trench isolation regions along and into the semiconductor layer, (d) depositing a sacrificial material on the first conductive layer, (e) etching the sacrificial material to form isolation channels, (f) forming two gate masks along lateral sides of the sacrificial material, (g) etching the first conductive layer to extend the channels to the insulating layer, (h) etching the sacrificial material to form a control channel, (i) etching the block of the first conductive layer, and (j) filling the control channel with a second conductive layer.

Abstract: A multi-function memory array that includes a DRAM distributed in several DRAM sectors, a Flash EEPROM distributed in several Flash EEPROM sectors, a data bus interconnecting the DRAM sectors and the Flash EEPROM sectors, and a plurality of memory access control circuitries. Each DRAM sector and Flash EEPROM sector can be accessed independently and data can be transferred between a DRAM sector and a Flash EEPROM sector. External data can also be written into either DRAM or Flash EEPROM. Flash EEPROM in one sector is distributed in rows and columns, and cells in each column are separated from the cells in an adjacent column by deep trench isolation regions.

Abstract: In a memory cell array, each memory cell includes a control gate disposed laterally adjacent a floating gate. The memory cells in each memory column are disposed inside a single well. The control gate and the floating gate are disposed between two diffusion regions. Each memory cell may be erased and programmed by applying a combination of voltages to the diffusion regions, the control gate, and the well.

Abstract: A programmable high speed routing switch is provided which has a lower ON-resistance so as to increase its gate oxide reliability. The routing switch includes a non-volatile memory cell (12) having a floating gate (FG). The floating gate is selectively charged and discharged to provide either a net positive potential or a net negative potential. The routing switch also includes a memory transistor (14), a pass gate transistor (16), and a poly load element (18). The source of the memory transistor is connected to a first power supply potential. The gate of the memory transistor is connected to the floating gate of the memory cell, and the drain thereof is connected to the gate of the pass gate transistor and to a first end of the poly load element. The drain of the pass gate transistor is connected to a first signal line (PG1) and the source of the pass gate transistor is connected to a second signal line (PG2). The second end of the poly load element is connected to a second power supply potential.