Patents by Inventor Ying Wei

Ying Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240153769
    Abstract: A first mask and a second mask are sequentially provided to perform a multi-step exposure and development processes. Through proper overlay design of the first mask and the second mask, conductive wirings having acceptable overlay offset are formed.
    Type: Application
    Filed: January 17, 2024
    Publication date: May 9, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jie Chen, Hsien-Wei Chen, Tzuan-Horng Liu, Ying-Ju Chen
  • Publication number: 20240155675
    Abstract: Techniques pertaining to adaptive transmission opportunity (TXOP) sharing for latency-sensitive traffic in wireless communications are described. An apparatus determines whether to activate an adaptive TXOP sharing mechanism with respect to a plurality of traffics having different latency requirements and pending transmission. In response to a positive determination, the apparatus utilizes the adaptive TXOP sharing mechanism in transmitting one or more traffics of the plurality of traffics associated with a plurality of stations (STAs) by performing either or both of: (i) selecting a candidate traffic from the one or more traffics of the plurality of traffics; and (ii) adjusting a transmission time of the candidate traffic in transmitting the candidate traffic during a TXOP.
    Type: Application
    Filed: September 13, 2023
    Publication date: May 9, 2024
    Inventors: Kuo-Wei Chen, Ying-You Lin
  • Publication number: 20240149494
    Abstract: A method for silicon carbide ingot peeling includes the steps of: placing the silicon carbide ingot between first and second suckers; having a pressing head disposed on a top surface of the first sucker to apply mechanical oscillatory energy to both the silicon carbide ingot and the second sucker through the first sucker; and, having an elastic element disposed under the second sucker to absorb part of the mechanical oscillatory energy to transmit longitudinal waves thereof to a modified layer of the silicon carbide ingot for propagating individually intermittent invisible cracks at the modified layer to break silicon carbide chains at different levels. Till the cracks connect together for forming a continuous crack across the silicon carbide ingot, a top portion of the silicon carbide ingot is then separable therefrom to form a wafer. In addition, an apparatus for silicon carbide ingot peeling is also provided.
    Type: Application
    Filed: February 13, 2023
    Publication date: May 9, 2024
    Inventors: WENG-JUNG LU, YING-FANG CHANG, PIN-YAO LEE, YI-WEI LIN
  • Publication number: 20240145421
    Abstract: Provided are a passivation layer for forming a semiconductor bonding structure, a sputtering target making the same, a semiconductor bonding structure and a semiconductor bonding process. The passivation layer is formed on a bonding substrate by sputtering the sputtering target; the passivation layer and the sputtering target comprise a first metal, a second metal or a combination thereof. The bonding substrate comprises a third metal. Based on a total atom number of the surface of the passivation layer, O content of the surface of the passivation layer is less than 30 at %; the third metal content of the surface of the passivation layer is less than or equal to 10 at %. The passivation layer has a polycrystalline structure. The semiconductor bonding structure sequentially comprises a first bonding substrate, a bonding layer and a second bonding substrate: the bonding layer is mainly formed by the passivation layer and the third metal.
    Type: Application
    Filed: October 27, 2023
    Publication date: May 2, 2024
    Inventors: Kuan-Neng CHEN, Zhong-Jie HONG, Chih-I CHO, Ming-Wei WENG, Chih-Han CHEN, Chiao-Yen WANG, Ying-Chan HUNG, Hong-Yi WU, CHENG-YEN HSIEH
  • Publication number: 20240142748
    Abstract: An optical system is provided. The optical system is used for disposing on an electronic device. The optical system includes a movable portion, a fixed portion, a first driving assembly, and a support module. The movable portion is used for connecting to an optical module. The fixed portion is affixed on the electronic device, and the movable portion is movable relative to the fixed portion. The first driving assembly is used for driving the movable portion to move relative to the fixed portion. The movable portion is movably connected to the fixed portion through the support module.
    Type: Application
    Filed: January 4, 2024
    Publication date: May 2, 2024
    Inventors: Ying-Jen WANG, Ya-Hsiu WU, Chen-Chi KUO, Chao-Chang HU, Yi-Ho CHEN, Che-Wei CHANG, Ko-Lun CHAO, Sin-Jhong SONG
  • Patent number: 11972981
    Abstract: A method for fabricating a semiconductor device having a substantially undoped channel region includes forming a plurality of fins extending from a substrate. In various embodiments, each of the plurality of fins includes a portion of a substrate, a portion of a first epitaxial layer on the portion of the substrate, and a portion of a second epitaxial layer on the portion of the first epitaxial layer. The portion of the first epitaxial layer of each of the plurality of fins is oxidized, and a liner layer is formed over each of the plurality of fins. Recessed isolation regions are then formed adjacent to the liner layer. The liner layer may then be etched to expose a residual material portion (e.g., Ge residue) adjacent to a bottom surface of the portion of the second epitaxial layer of each of the plurality of fins, and the residual material portion is removed.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: April 30, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Ying-Keung Leung
  • Patent number: 11969448
    Abstract: A probiotic composition for improving an effect of a chemotherapeutic drug of Gemcitabine on inhibiting pancreatic cancer is disclosed in the present disclosure. The probiotic composition comprises an effective amount of Lactobacillus paracasei GMNL-133, an effective amount of Lactobacillus reuteri GMNL-89, and a pharmaceutically acceptable carrier, wherein the Lactobacillus paracasei GMNL-133 was deposited in the China Center for Type Culture Collection on Sep. 26, 2011 under an accession number CCTCC NO. M 2011331, and the Lactobacillus reuteri GMNL-89 was deposited in the China Center for Type Culture Collection on Nov. 19, 2007 under an accession number CCTCC NO. M 207154. A method for improving the effect of the chemotherapeutic drug of Gemcitabine on inhibiting pancreatic cancer is further disclosed in the present disclosure.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: April 30, 2024
    Assignee: GENMONT BIOTECH INC.
    Inventors: Wan-Hua Tsai, I-ling Hsu, Shan-ju Hsu, Wen-ling Yeh, Ming-shiou Jan, Wee-wei Chieng, Li-jin Hsu, Ying-chun Lai
  • Patent number: 11969915
    Abstract: The present application disclosures a double production line and a rapid prefabrication process of a segmental beam. The double production line including two production machine and a track system provided on the construction ground; the production machine includes a fixed end mold, two side molds, a bottom mold trolley, a middle internal mold trolley and two side internal mold trolley; two side molds are positioned on two sides of the fixed end mold respectively, the fixed end mold and two side molds together define a pouring position with an end opening, two openings of the pouring position are arranged facing each other; the track system includes a transverse track and a longitudinal track communicated with each other, two pouring positions are both positioned in the extension path of the transverse track, and the longitudinal track is positioned between two pouring positions.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: April 30, 2024
    Assignees: CHINA RAILWAY GUANGZHOU ENGINEERING GROUP CO., LTD., China Railway Guangzhou Engineering Group Real Estate Co., Ltd.
    Inventors: Xiao Zhou, Xiaofeng Deng, Yongguang Chen, Zhouyu Xie, Gaofei Wei, Jiawei Yang, Ping Zhang, Beibei Cheng, Wenqiang Zheng, Ying Wang, Yuan Xu
  • Publication number: 20240136293
    Abstract: Provided are a package structure having a joint structure and a method of forming the same. The package structure includes: a first under bump metallurgy (UBM) structure disposed on a first dielectric layer, wherein the first UBM structure at least comprises: a barrier layer embedded in the first dielectric layer; and an upper metal layer disposed over the barrier layer, wherein a sidewall of the barrier layer is laterally offset outward from a sidewall of the upper metal layer, and a portion of a top surface of the barrier layer is exposed by the first dielectric layer; and a solder layer disposed on the first UBM structure and contacting the upper metal layer.
    Type: Application
    Filed: January 31, 2023
    Publication date: April 25, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Wei Wu, Wen-Chih Chiou, Ying-Ching Shih
  • Publication number: 20240136226
    Abstract: An ammonium fluoride gas may be used to form a protection layer for one or more interlayer dielectric layers, one or more insulating caps, and/or one or more source/drain regions of a semiconductor device during a pre-clean etch process. The protection layer can be formed through an oversupply of nitrogen trifluoride during the pre-clean etch process. The oversupply of nitrogen trifluoride causes an increased formation of ammonium fluoride, which coats the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) with a thick protection layer. The protection layer protects the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) during the pre-clean process from being etched by fluorine ions formed during the pre-clean process.
    Type: Application
    Filed: January 2, 2024
    Publication date: April 25, 2024
    Inventors: Li-Wei CHU, Ying-Chi SU, Yu-Kai CHEN, Wei-Yip LOH, Hung-Hsu CHEN, Chih-Wei CHANG, Ming-Hsing TSAI
  • Publication number: 20240122856
    Abstract: A method of preparing polylactic acid (PLA) microsphere and polylactic-co-glycolic acid (PLGA) microsphere is provided, including the following steps. A first solution is provided, including polylactic acid or polylactic-co-glycolic acid and an organic solvent. A second solution is provided, including polyvinyl alcohol, sodium carboxymethyl cellulose and an aqueous solution. The first solution is added to the second solution and, at the same time, the second solution is agitated until polylactic acid is solidified to form a plurality of polylactic acid microspheres, or until polylactic-co-glycolic acid is solidified to form a plurality of polylactic-co-glycolic acid microspheres. The polylactic acid microspheres or polylactic-co-glycolic acid microspheres are collected.
    Type: Application
    Filed: December 27, 2023
    Publication date: April 18, 2024
    Inventors: Ming-Thau SHEU, Yu-Ying HSU, Yu-De SU, Yu-Hsuan LIU, Pu-Sheng WEI
  • Publication number: 20240128211
    Abstract: Some implementations described herein provide techniques and apparatuses for a stacked semiconductor die package. The stacked semiconductor die package may include an upper semiconductor die package above a lower semiconductor die package. The stacked semiconductor die package includes one or more rows of pad structures located within a footprint of a semiconductor die of the lower semiconductor die package. The one or more rows of pad structures may be used to mount the upper semiconductor die package above the lower semiconductor die package. Relative to another stacked semiconductor die package including a row of dummy connection structures adjacent to the semiconductor die that may be used to mount the upper semiconductor die package, a size of the stacked semiconductor die package may be reduced.
    Type: Application
    Filed: April 27, 2023
    Publication date: April 18, 2024
    Inventors: Chih-Wei WU, An-Jhih SU, Hua-Wei TSENG, Ying-Ching SHIH, Wen-Chih CHIOU, Chun-Wei CHEN, Ming Shih YEH, Wei-Cheng WU, Der-Chyang YEH
  • Patent number: 11962301
    Abstract: Technologies for low jitter and low power ring oscillators with multi-phase signal reassembly are described. A ring oscillator circuit includes a ring oscillator with a set of M delay stages, each stage outputs a phase signal, where M is a positive integer greater than one. The ring oscillator circuit includes a phase selector circuit coupled to the ring oscillator. The phase selector circuit can receive M phase signals from the ring oscillator and generate N phase signals based on the M phase signals, where N is a positive integer less than M.
    Type: Grant
    Filed: August 18, 2022
    Date of Patent: April 16, 2024
    Assignee: Nvidia Corporation
    Inventors: Chun-Ju Shen, Chien-Heng Wong, Ying Wei
  • Publication number: 20240120812
    Abstract: An integrated motor and drive assembly is disclosed and includes a housing, a motor and a drive. The housing includes a motor-accommodation portion and a drive-accommodation portion. The drive includes a power board and a control board. The power board is made of a high thermal conductivity substrate and includes a power element and an encoder disposed on the first side, the first side faces the motor, the power board and the motor are stacked along a first direction, and the second side contacts the housing to from a heat-dissipating route. The control board is disposed adjacent to the power board. The control board and the power board are arranged along a second direction perpendicular to the first direction, and the first direction is parallel to an axial direction of the motor. A part of the power board and a part of the control board are directly contacted to form an electrical connection.
    Type: Application
    Filed: July 17, 2023
    Publication date: April 11, 2024
    Inventors: Chi-Hsiang Kuo, Yi-Yu Lee, Zuo-Ying Wei, Yuan-Kai Liao, Wen-Cheng Hsieh
  • Patent number: 11951560
    Abstract: The present disclosure provides a wire and arc additive manufacturing (WAAM) method for a titanium alloy. The method includes the following steps: step 1: performing a WAAM process assisted by cooling and rolling; step 2: milling side and top surfaces of an additive part; step 3: performing, by friction stir processing (FSP) equipment, an FSP process on the additive part, and applying cooling and rolling to a side wall of the additive part through a cooling and rolling device during the FSP process; step 4: finish-milling the top surface of the additive part for a WAAM process in the next step; and step 5: repeating the above steps cyclically until final forming of the part is finished. This WAAM method completely breaks dendritic structures and refines grains in the WAAM process of the titanium alloy, thereby effectively repairing defects such as pores and cracks.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: April 9, 2024
    Assignee: NORTHEASTERN UNIVERSITY
    Inventors: Changshu He, Jingxun Wei, Ying Li, Zhiqiang Zhang, Ni Tian, Gaowu Qin
  • Patent number: 11953156
    Abstract: Disclosed are a corrugated plate having a smooth top surface and drawbeads, and a storage container. The corrugated plate includes a corrugated plate body, a longitudinal corrugation, a transverse corrugation, and an intersection portion. The intersection portion includes a smooth top surface and four drawbeads extending from the top surface to the corrugated plate body. The top surface transitions to the drawbeads smoothly. An overall extension direction of each of the drawbeads intersects a transverse direction, a longitudinal direction, and a height direction perpendicular to the corrugated plate body.
    Type: Grant
    Filed: August 30, 2023
    Date of Patent: April 9, 2024
    Assignee: SINOTECH ENERGY CO., LTD.
    Inventors: Ying Wei, Xiangao Feng, Wei He, Kang Wang, Jinlin Zhang
  • Patent number: 11955861
    Abstract: A stator of a brushless motor is disclosed which includes a stator core, an insulating frame arranged on the stator core, and a plurality of windings wound around the insulating frame. The stator core includes a ring-shaped yoke part and a pole part mounted to the radial inner side of the yoke part. The pole part includes a plurality of teeth spaced-apart from each other along the circumferential direction, and a ring-shaped portion arranged at and connected to the radial inner side of the teeth. The radial outer sides of the teeth abut against the radial inner side of the yoke part. The insulating frame is arranged on the pole part. A plurality of power terminals are fixed to one axial end of the insulating frame and respectively electrically connected to the windings.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: April 9, 2024
    Assignee: JOHNSON ELECTRIC INTERNATIONAL AG
    Inventors: Ying Feng, Yick Kun Kenny Tsui, Ping Wo Poon, Kam Ting Ko, Siu Kin Tam, Da Wei Zhou
  • Patent number: 11955459
    Abstract: A package structure is provided. The package structure includes a first die and a second die, a dielectric layer, a bridge, an encapsulant, and a redistribution layer structure. The dielectric layer is disposed on the first die and the second die. The bridge is electrically connected to the first die and the second die, wherein the dielectric layer is spaced apart from the bridge. The encapsulant is disposed on the dielectric layer and laterally encapsulating the bridge. The redistribution layer structure is disposed over the encapsulant and the bridge. A top surface of the bridge is in contact with the RDL structure.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Hang Liao, Chih-Wei Wu, Jing-Cheng Lin, Szu-Wei Lu, Ying-Ching Shih
  • Patent number: 11957064
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a spacer adjacent to the MTJ, a liner adjacent to the spacer, and a first metal interconnection on the MTJ. Preferably, the first metal interconnection includes protrusions adjacent to two sides of the MTJ and a bottom surface of the protrusions contact the liner directly.
    Type: Grant
    Filed: October 18, 2022
    Date of Patent: April 9, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
  • Patent number: 11948641
    Abstract: A memory device includes a memory array including a cell, and a controller coupled to the memory array. The controller is configured to control sequentially applying programming voltage pulses to the cell. A pulse width of each of the programming voltage pulses decreases as a pulse count of the programming voltage pulses increases.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: April 2, 2024
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Ying Huang, Hongtao Liu, Qiguang Wang, Wenzhe Wei