Abstract: A server power saving system includes a motherboard and a backplane. The motherboard includes a CPLD, a basic I/O control chip electrically connected with the CPLD, and a clock chip electrically connected with the CPLD. The basic I/O control chip includes a basic I/O control program The backplane includes a HD microcontroller electrically connected with the CPLD and a HD connection port electrically connected with the HD microcontroller and the clock chip. The HD microcontroller sends clock enable signal to the CPLD when a HD is electrically connected with the HD connection port. The CPLD transmits clock enable signal to the basic I/O control chip. The basic I/O control chip sends confirmation signal to the CPLD according to clock enable signal, and the CPLD determines whether to drive the clock chip to send clock signal to the HD connection port according to a content of confirmation signal.

Abstract: The present disclosure provides a server system that comprises: a CPLD comprising a first firmware and a first serial peripheral interface; and a serial peripheral read-only memory comprising a second firmware and a second serial peripheral interface; wherein the first serial peripheral interface electrically connects to the second serial peripheral interface through a serial peripheral signal. The CPLD detects the first firmware and the second firmware when the server system is booting. The CPLD sets the first firmware as a main firmware and the first firmware is used for a booting of the server system when the first firmware is detected. The CPLD sets the second firmware as the main firmware when the first firmware is not detected and the second firmware is detected. Through the technical solution of the present disclosure, the server can ensure the normal operation of the system even the CPLD firmware has a problem.

Abstract: A server power saving system includes a motherboard and a backplane. The motherboard includes a CPLD, a basic I/O control chip electrically connected with the CPLD, and a clock chip electrically connected with the CPLD. The basic I/O control chip includes a basic I/O control program The backplane includes a HD microcontroller electrically connected with the CPLD and a HD connection port electrically connected with the HD microcontroller and the clock chip. The HD microcontroller sends clock enable signal to the CPLD when a HD is electrically connected with the HD connection port. The CPLD transmits clock enable signal to the basic I/O control chip. The basic I/O control chip sends confirmation signal to the CPLD according to clock enable signal, and the CPLD determines whether to drive the clock chip to send clock signal to the HD connection port according to a content of confirmation signal.

Abstract: A BIOS switching device adapted to a server comprises a switching module, a CPLD, a storage module and a BMC. The switching module comprises a movable switching element locating at a first position or at a second position and a plurality of hardware pins. The hardware pins are logical low when the switching element locates at the second position and remains unchanged logical level when the switching element locates at the first position. The CPLD electrically connects to the switching module, comprising a plurality of input signals respectively coupled to the plurality of hardware pins. The CPLD generates an output signal according to the plurality of input signals. The BMC activates a first BIOS or a second BIOS from the storage module according to the logical level of the output signal of the CPLD.

Abstract: An electronic device having a temperature management function includes a platform controller hub (PCH), a complex programmable logic device (CPLD) and a hardware monitor. The PCH includes a first temperature sensor for sensing the first temperature of the PCH. The CPLD includes a memory and is coupled to the PCH. The CPLD reads the first temperature sensed by the first temperature sensor and saves it in the memory. The CPLD searches for an offset value in the memory and generates a device temperature according to the offset value and the first temperature. The hardware monitor is coupled to the CPLD and reads the device temperature.

Abstract: A chip programming device comprises a chip socket and a protecting circuit. The chip socket is configured to accommodate a chip to be programmed, is electrically connected with a circuit board, and comprises a power terminal and a ground terminal which are configured to connect to the chip. The protecting circuit is disposed on the circuit board, and comprises a power input terminal, an enable signal input terminal and a power output terminal which is electrically connected to the power terminal of the chip socket. The protecting circuit receives a power signal via the power input terminal, receives an enable signal via the enable signal input terminal, provides the power signal to the chip socket via the power output terminal when the enable signal has a first electric potential, and terminates the power signal to the chip socket when the enable signal has a second electric potential.

Abstract: A computer has a platform controller hub (PCH), a field replaceable unit (FRU), a memory, a complex programmable logic device (CPLD) and a basic input output system (BIOS) chip. The PCH has a first port and a second port. The FRU and the memory are both electrically connected to the first port of the PCH. The CPLD is electrically connected to the second port of the PCH, and used for detecting an indicating signal from the second port to selectively generate a reset signal. The BIOS chip is electrically connected to the PCH, the FRU, and the CPLD, and used for making the computer rebooted in a manufacturer mode or a normal mode according to the reset signal.

Abstract: A BIOS switching device adapted to a server comprises a switching module, a CPLD, a storage module and a BMC. The switching module comprises a movable switching element locating at a first position or at a second position and a plurality of hardware pins. The hardware pins are logical low when the switching element locates at the second position and remains unchanged logical level when the switching element locates at the first position. The CPLD electrically connects to the switching module, comprising a plurality of input signals respectively coupled to the plurality of hardware pins. The CPLD generates an output signal according to the plurality of input signals. The BMC activates a first BIOS or a second BIOS from the storage module according to the logical level of the output signal of the CPLD.

Abstract: A chip programming device comprises a chip socket and a protecting circuit. The chip socket is configured to accommodate a chip to be programmed, is electrically connected with a circuit board, and comprises a power terminal and a ground terminal which are configured to connect to the chip. The protecting circuit is disposed on the circuit board, and comprises a power input terminal, an enable signal input terminal and a power output terminal which is electrically connected to the power terminal of the chip socket. The protecting circuit receives a power signal via the power input terminal, receives an enable signal via the enable signal input terminal, provides the power signal to the chip socket via the power output terminal when the enable signal has a first electric potential, and terminates the power signal to the chip socket when the enable signal has a second electric potential.

Abstract: In a system and a method for controlling temperatures of a computer, an infrared induction module and a temperature-detecting module are applied to obtain position information and temperature information of a device module, and the position information and the temperature information are further analyzed and judged by a baseboard management controller to carry out different control means for the device module under different operation status and temperature conditions. Through the system and the method, the device module can be kept in operating under an operation temperature less than a predetermined temperature, so as to ensure the normal operation of the device module and to further promote the efficiency of test, maintenance and repair.

Abstract: A fan monitoring system includes a first fan, a complex programmable logic device and a fan status notification module. The first fan operates according to a signal of first fan rotating speed and generates a first impulse signal having a first impulse frequency value. The complex programmable logic device counts a time period of continuously receiving the first impulse signal having the first impulse frequency value remaining consistent. The complex programmable logic device determines that the first fan operates abnormally and generates a first fan error signal when determining that the first impulse frequency value reaches a first peak and the time period of continuously receiving the first impulse signal having the first impulse frequency value remaining consistent is greater than a first predetermined time value. The fan status notification module displays a first fan error status notification when receiving the first fan error signal.

Abstract: The present disclosure provides a computer system, which includes a controlling unit and a memory. The controlling unit stores a first boot firmware, wherein the controlling unit has a first port. The memory is coupled to the first port of the controlling unit, wherein the memory stores a second boot firmware. When the computer is booted, the controlling unit detects the states of the first boot firmware and the second boot firmware, so as to select the first boot firmware or select to access the memory through the first port. Therefore, the working efficiency of the computer system is improved and the convenience of the usage is increased.

Abstract: In the system, a buffer and a multiplexer are electrically connected to an I2C interface and a control interface of a PCH. A plurality of memory are electrically connected to the buffer and corresponding to a first I2C address respectively. A plurality of card slots are electrically connected to the multiplexer for connecting to a function card so that the function card is corresponding to a second I2C address. When the first I2C address is distinct to the second I2C address, the PCH triggers the multiplexer to be enabled through the control interface to have the function card electrically connected to the PCH through the I2C interface. When the first I2C address is the same as the second I2C address, the PCH triggers the multiplexer or the buffer to be disabled through the control interface to have the function card or the memories electrically connected to the PCH through the I2C interface.

Abstract: A computer system including a PCH (platform controller hub), a CPLD (complex programmable logic device), a first switch and a processor, and a control method are provided to control the operation frequency of the processor. The CPLD is coupled to the PCH and the first switch. The processor is coupled to the first switch. The PCH produces and outputs a second control signal according to the first firmware and a first control signal from a command input unit. The CPLD produces and outputs a third control signal according to the second firmware and the second control signal. The first switch receives the third control signal and is turned on to output a triggering signal when the third control signal is valid. The processor includes a PROCHOT pin. The processor receives the triggering signal and triggers the PROCHOT pin for frequency control.

Abstract: A computer has a platform controller hub (PCH), a field replaceable unit (FRU), a memory, a complex programmable logic device (CPLD) and a basic input output system (BIOS) chip. The PCH has a first port and a second port. The FRU and the memory are both electrically connected to the first port of the PCH. The CPLD is electrically connected to the second port of the PCH, and used for detecting an indicating signal from the second port to selectively generate a reset signal. The BIOS chip is electrically connected to the PCH, the FRU, and the CPLD, and used for making the computer rebooted in a manufacturer mode or a normal mode according to the reset signal.

Abstract: An electronic device having a temperature management function includes a platform controller hub (PCH), a complex programmable logic device (CPLD) and a hardware monitor. The PCH includes a first temperature sensor for sensing the first temperature of the PCH. The CPLD includes a memory and is coupled to the PCH. The CPLD reads the first temperature sensed by the first temperature sensor and saves it in the memory. The CPLD searches for an offset value in the memory and generates a device temperature according to the offset value and the first temperature. The hardware monitor is coupled to the CPLD and reads the device temperature.

Abstract: A power failure monitoring system and a method are disclosed herein, where the power failure monitoring system includes a motherboard, a board, a complex programmable logic device (CPLD) and a baseboard management controller (BMC) module. The motherboard includes a central processing unit (CPU) power and a non-CPU power. The board includes a board power. The BMC module includes a register that is electrically coupled to the CPLD. The CPLD is configured to execute a shutdown process when power failure occurs, identify a power failure type, and determine whether to execute a restart process according to the power failure type. If the restart process is executed and a count of the restart process reaches a predetermined count, the CPLD records lock information in the register. The BMC module is configured to record the count of the restart process, and execute a lock process according to the lock information.

Abstract: A power source protection device and a power source protection method are disclosed herein. The power source protection device includes a power supply, a power source managing unit and a signal sending unit. The power supply provides a DC input voltage. The power source managing unit receives the DC input voltage, and when a determining voltage related to the input voltage is larger than a set voltage, enters a startup state and outputs a supply voltage. After receiving the supply voltage, the power source managing unit transforms the DC input voltage into a standby power output voltage and provides the standby power output voltage when the signal sending unit sends a control signal to the power source managing unit within an enabling time. VVhen it has not received the control signal within the enabling time, the power source managing unit enters a shutdown state.

Abstract: In the updating system, the CPLD has an original firmware version data and a PCH of a processing chip includes a storage which stores an updating identification code table and at least one updating firmware data. The updating identification code table has at least one updating identification code which is corresponded to the updating firmware data respectively. A processing unit of the processing chip has an identification code and an updating program. In the updating method, a first step is provided to capture the updating identification code table after the updating program is triggered. A second step is provided to capture the updating firmware data when the identification code is same as the updating identification code. A third step is provided to replace the original firmware version data from the updating firmware data through the PCH.

Abstract: In the system, a buffer and a multiplexer are electrically connected to an I2C interface and a control interface of a PCH. A plurality of memory are electrically connected to the buffer and corresponding to a first I2C address respectively. A plurality of card slots are electrically connected to the multiplexer for connecting to a function card so that the function card is corresponding to a second I2C address. When the first I2C address is distinct to the second I2C address, the PCH triggers the multiplexer to be enabled through the control interface to have the function card electrically connected to the PCH through the I2C interface. When the first I2C address is the same as the second I2C address, the PCH triggers the multiplexer or the buffer to be disabled through the control interface to have the function card or the memories electrically connected to the PCH through the I2C interface.