Abstract: Embodiments of this application provide a method for coding in a wireless communication network. A communication device interleave a first bit sequence to obtain a first interleaved sequence having sequence number starting with a sequence number of 0, wherein the first bit sequence comprises bits for indicating timing, wherein the bits for indicating timing comprises a set of bits for indicating synchronization signal block index (SSBI); wherein the set of bits for indicating SSBI are placed in positions indicated by sequence numbers of 2, 3 and 5 in the first interleaved sequence. The devices add d first CRC bits on the first interleaved sequence to obtain a second bit sequence, interleave on the second bit sequence according to an interleave pattern to obtain a second interleaved sequence, and polar encode the second interleaved sequence to obtain the encoded sequence.

Abstract: This application relates to the field of wireless communications technologies, and discloses an encoding method and apparatus, to improve accuracy of reliability calculation and ordering for polarized channels. The method includes: obtaining a first sequence used to encode K to-be-encoded bits, where the first sequence includes sequence numbers of N polarized channels, the first sequence is same as a second sequence or a subset of the second sequence, the second sequence comprises sequence numbers of Nmax polarized channels, and the second sequence is the sequence shown in Sequence Q11 or Table Q11, K is a positive integer, N is a positive integer power of 2, n is equal to or greater than 5, K?N, Nmax=1024; selecting sequence numbers of K polarized channels from the first sequence; and performing polar code encoding on K the to-be-encoded bits based on the selected sequence numbers of the K polarized channels.

Abstract: The present disclosure relates to artificial intelligence (AI) operation processing methods apparatuses. One example method includes obtaining a first group identifier, obtaining a trigger message sent by a network device, where the trigger message includes first control information, the first control information indicates a first time-frequency resource, the first time-frequency resource carries N pieces of first scheduling information, each of the N pieces of first scheduling information includes a respective second group identifier and respective AI operation information and indicates a terminal device in a user group indicated by the respective second group identifier to perform an AI operation corresponding to the respective AI operation information, determining target AI operation information when the first group identifier matches a target group identifier, and starting a target AI operation based on the target AI operation information.

Abstract: The present invention relates to a metalized waveguide interface (1) for providing a galvanically isolated waveguide connection for a propagating signal, between a standardized waveguide (2) and a, to the standardized waveguide non-compatible, metalized chip-level waveguide (3). The metalized waveguide interface (1) is configured such that a first open-ended quarter wavelength waveguide (31) and a second open-ended quarter wavelength waveguide (32) is obtained along the directions d1 and d2, respectively, when the metalized chip-level waveguide (3) is mounted on the support surface (5). The interface is further configured such that third open-ended quarter wavelength waveguide (33) is obtained between the third surface portion (9) and the metalized chip-level waveguide (3) when the metalized chip-level waveguide (3) is mounted on the support surface (5).

Abstract: Frequency multipliers (300) for generating a differential output signal from a single-ended input signal are disclosed. The frequency multiplier comprises a single-ended input (Pin(f0)) to receive the input signal with a frequency of f0 and differential outputs (+/?Pout(2nf0)) to provide the differential output signals. The frequency multiplier further comprises a first signal branch (301) connected to the single-ended input and one of the differential outputs (+Pout(2nf0)). The first signal branch comprises a first low pass or bandpass filter with a center frequency of f0 (L/BPF1), a first nonlinear component (NC1) and a first high pass or bandpass filter with a center frequency of 2nf0 (H/BPF1). The frequency multiplier further comprises a second signal branch connected to the single-end input and another one of the differential outputs (?Pout(2nf0)).

Abstract: The present invention relates to a metalized waveguide interface (1) for providing a galvanically isolated waveguide connection for a propagating signal, between a standardized waveguide (2) and a, to the standardized waveguide non-compatible, metalized chip-level waveguide (3). The metalized waveguide interface (1) is configured such that a first open-ended quarter wavelength waveguide (31) and a second open-ended quarter wavelength waveguide (32) is obtained along the directions d1 and d2, respectively, when the metalized chip-level waveguide (3) is mounted on the support surface (5). The interface is further configured such that third open-ended quarter wavelength waveguide (33) is obtained between the third surface portion (9) and the metalized chip-level waveguide (3) when the metalized chip-level waveguide (3) is mounted on the support surface (5).

Abstract: The present invention relates to a metalized waveguide interface (1) for providing a galvanically isolated waveguide connection for a propagating signal, between a standardized waveguide (2) and a, to the standardized waveguide non-compatible, metalized chip-level waveguide (3). The metalized waveguide interface (1) is configured such that a first open-ended quarter wavelength waveguide (31) and a second open-ended quarter wavelength waveguide (32) is obtained along the directions d1 and d2, respectively, when the metalized chip-level waveguide (3) is mounted on the support surface (5). The interface is further configured such that third open-ended quarter wavelength waveguide (33) is obtained between the third surface portion (9) and the metalized chip-level waveguide (3) when the metalized chip-level waveguide (3) is mounted on the support surface (5).

Abstract: An active antenna (100, 200, 300) comprising a driving loop with first (103) and second (105) sections, each of which extends between end points. Each end point of each section (103, 105) is connected to the closest end point of the other section by a reflection amplifier (101, 106). One reflection amplifier (106) comprises differential ports for signals to/from the active antenna. The active antenna also comprises a passive loop with first (107) and second (108) sections, each of which extends between end points. Each end point of each section (107, 108) is connected to the closest end point of the other section by a reflection amplifier (102, 104). The driving loop and the passive loop extend in parallel to each other and the first and the second section (103, 105; 107, 108) of each of the loops form separated complementary parts of a closed geometrical shape and are built in open waveguide technology.

Abstract: A frequency converter (100, 200, 300, 500, 600) comprising a first mixer (105) arranged to receive a first and a second input signal and to have as its output the sum and the difference of the first and second input signals. The frequency converter (100, 200, 300, 500, 600) also comprises generating means (120) for generating the second input signal and for receiving the output signal of the first mixer (105) and multiplying it by a signal at a frequency which is two times the frequency of the second input signal, thereby generating a product. The frequency converter (100, 200, 300, 500, 600) also comprises adding means (110) for obtaining the sum of this product and the output signal from the first mixer.

Abstract: A duplex unit allowing simultaneous transmission and reception of microwave signals on at least partly overlapping frequency bands, comprising an interference canceller unit and a control unit, the duplex unit being arranged to receive a transmit signal and to output a first part of the transmit signal at an antenna port, the duplex unit further being arranged to receive a receive signal comprising a payload signal at the antenna port, and to output a combination of the receive signal and a filtered transmit signal as an interference suppressed receive signal of the duplex unit.

Abstract: A frequency converter (100, 200, 300, 500, 600) comprising a first mixer (105) arranged to receive a first and a second input signal and to have as its output the sum and the difference of the first and second input signals. The frequency converter (100, 200, 300, 500, 600) also comprises generating means (120) for generating the second input signal and for receiving the output signal of the first mixer (105) and multiplying it by a signal at a frequency which is two times the frequency of the second input signal, thereby generating a product. The frequency converter (100, 200, 300, 500, 600) also comprises adding means (110) for obtaining the sum of this product and the output signal from the first mixer.

Abstract: A duplex unit allowing simultaneous transmission and reception of microwave signals on at least partly overlapping frequency bands, comprising an interference canceller unit and a control unit, the duplex unit being arranged to receive a transmit signal and to output a first part of the transmit signal at an antenna port, the duplex unit further being arranged to receive a receive signal comprising a payload signal at the antenna port, and to output a combination of the receive signal and a filtered transmit signal as an interference suppressed receive signal of the duplex unit.

Abstract: An active antenna (100, 200, 300) comprising a driving loop with first (103) and second (105) sections, each of which extends between end points. Each end point of each section (103, 105) is connected to the closest end point of the other section by a reflection amplifier (101, 106). One reflection amplifier (106) comprises differential ports for signals to/from the active antenna. The active antenna also comprises a passive loop with first (107) and second (108) sections, each of which extends between end points. Each end point of each section (107, 108) is connected to the closest end point of the other section by a reflection amplifier (102, 104). The driving loop and the passive loop extend in parallel to each other and the first and the second section (103, 105; 107, 108) of each of the loops form separated complementary parts of a closed geometrical shape and are built in open waveguide technology.

Abstract: Embodiments of the present invention relate to a self injection locked voltage controlled oscillator arrangement, a pair of coupled first and second voltage controlled oscillator devices are arranged on a chip, an amplifier device is arranged on the same of the refection type chip, and an off-chip delay line is arranged with one terminal connected to an output terminal of the coupled first and second voltage controlled oscillator devices, and on terminal adapted to reflect a signal from the output terminal, the amplifier device being arranged to amplify an injection signal from said output terminal and to supply the amplified injection signal to one of said first and second voltage controlled oscillation devices to provide a VCO arrangement that exhibits low phase noise and a small size.

Abstract: A combination mixer arrangement comprising a first mixer and a second mixer coupled in parallel between first and second input ports and an output port. The mixers are arranged to be driven simultaneously by an input signal provided at the second input port. They are de-coupled, so a bias voltage applied at the first input port provides dc bias simultaneously for the mixers to enable gain expansion of the first mixer responsive to an increase in said input signal and thereby an improved linearity for the combination mixer arrangement.

Abstract: Embodiments of the present invention relate to a self injection locked voltage controlled oscillator arrangement, a pair of coupled first and second voltage controlled oscillator devices are arranged on a chip, an amplifier device is arranged on the same of the refection type chip, and an off-chip delay line is arranged with one terminal connected to an output terminal of the coupled first and second voltage controlled oscillator devices, and on terminal adapted to reflect a signal from the output terminal, the amplifier device being arranged to amplify an injection signal from said output terminal and to supply the amplified injection signal to one of said first and second voltage controlled oscillation devices to provide a VCO arrangement that exhibits low phase noise and a small size.

Abstract: In a voltage controlled oscillator circuit comprising two transistors, the first terminals of each said two transistors, are coupled together and to a supply voltage, two interconnected resonator units, and each of said two resonator units couples a respective second terminal of said two transistors to third terminals of both said transistors.

Abstract: A combination mixer arrangement comprising a first mixer and a second mixer coupled in parallel between first and second input ports and an output port. The mixers are arranged to be driven simultaneously by an input signal provided at the second input port. They are de-coupled, so a bias voltage applied at the first input port provides dc bias simultaneously for the mixers to enable gain expansion of the first mixer responsive to an increase in said input signal and thereby an improved linearity for the combination mixer arrangement.

Abstract: In a voltage controlled oscillator circuit comprising two transistors, the first terminals of each said two transistors, are coupled together and to a supply voltage, two interconnected resonator units, and each of said two resonator units couples a respective second terminal of said two transistors to third terminals of both said transistors.

Abstract: The present invention relates to a voltage-to-current transconductance stage arrangement comprising a single-ended input, an emitter-coupled pair of transistors, comprising a first transistor and a second transistor, the emitter of a third transistor, being connected to the collector of said first transistor, and differential output. It further comprises at least one common-collector transistor comprising a fourth transistor connected to the base of said second transistor preferably or optionally also and a fifth transistor connected to the base of said third transistor. The size of said fourth, or fourth and fifth transistors considerably exceed the sizes of said second and third transistors. They are biased at ‘off-state’. An extra inductor at the collector of the transistor may be applied to further increase linearity.