Abstract: In one example, an apparatus comprises a power stage having a first power stage input, a second power stage input, and a power stage output. The apparatus also comprises a modulator circuit having a first ramp input, a second ramp input, a modulator input, a first modulator output, and a second modulator output, the first modulator output coupled to the first power stage input, and the second modulator output coupled to the second power stage input. The apparatus also comprises a multi-level ramp generator having a first ramp output and a second ramp output, the first ramp output coupled to the first ramp input, and the second ramp output coupled the second ramp input.

Abstract: A device includes a first ramp generator having a first ramp generator output configured to provide a first ramp, a second ramp generator having a second ramp generator output configured to provide a second ramp, and a third ramp generator having a third ramp generator output configured to provide a third ramp. The first ramp is a sawtooth voltage waveform having a first common mode voltage and a first peak-to-peak voltage. The second ramp is a sawtooth voltage waveform having a second common mode voltage and a second peak-to-peak voltage. The third ramp is a sawtooth voltage waveform having a third common mode voltage and a third peak-to-peak voltage. A frequency of the second ramp is approximately equal to a frequency of the third ramp, and the frequency of the third ramp is approximately double a frequency of the first ramp.

Abstract: A power converter including a piezoelectric resonator. The power converter includes a first transistor coupled between an input terminal and a first plate of the piezoelectric resonator, and a second transistor coupled between the first plate of the piezoelectric resonator and an output terminal. A load may be coupled at the output terminal. Controller circuitry has inputs coupled to the input node, the output node, and to the first plate of the piezoelectric resonator, and outputs coupled to control terminals of the first and second transistors. The controller circuitry operates to turn on the first transistor responsive to a comparison of voltages at the first plate and the input terminal, turn on the second transistor responsive to a comparison of voltages at the first plate and the output terminal, and turn off one of the first and second transistors responsive to an output level at the output terminal.

Abstract: A switching amplifier includes a first portion of a power stage; a second portion of a power stage; a pulse-width modulation (PWM) control loop coupled to control inputs of the first portion of the power stage; and a linear amplifier coupled to control inputs of the second portion of the power stage. The PWM control loop controls a first switch and a second switch of the first portion of the power stage. Between current terminals of the first switch and the second switch is a first signal output of the switching amplifier. The linear amplifier controls a third switch and a fourth switch of the second portion of the power stage. Between current terminals of the third switch and the fourth switch is a second signal output of the switching amplifier.

Abstract: Described embodiments include an audio amplifier circuit that includes a first amplifier having a differential first amplifier input adapted to be coupled to an audio input source, a multiplexer having first and second mux inputs, a control input and a mux output. The first mux input is coupled to the differential amplifier output. There is a signal generator having a generator input coupled to the mux output. There is also a driver circuit having a driver circuit input and a driver circuit output, the driver circuit input coupled to the generator output, and a second amplifier having a first error input coupled to a current sense terminal that is configured to provide a voltage proportional to a current supplied from a power supply terminal, and a second error input coupled to a current limit terminal configured to provide a reference voltage proportional to a current limit value.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to generate a modulation protocol to output audio. An example apparatus includes a modulation circuit including a first input, a second input, a first output, and a second output; a first gate coupled to the first output of the modulation circuit; a second gate coupled to the second output of the modulation circuit; a first multiplexer including a first input coupled to the first output of the modulation circuit, a second input coupled to the output of the second gate, and an output coupled to a first switch; and a second multiplexer including a first input coupled to the second output of the modulation circuit, a second input coupled to the output of the first gate, and an output coupled to a second switch.

Abstract: A device includes a first ramp generator having a first ramp generator output configured to provide a first ramp, a second ramp generator having a second ramp generator output configured to provide a second ramp, and a third ramp generator having a third ramp generator output configured to provide a third ramp. The first ramp is a sawtooth voltage waveform having a first common mode voltage and a first peak-to-peak voltage. The second ramp is a sawtooth voltage waveform having a second common mode voltage and a second peak-to-peak voltage. The third ramp is a sawtooth voltage waveform having a third common mode voltage and a third peak-to-peak voltage. A frequency of the second ramp is approximately equal to a frequency of the third ramp, and the frequency of the third ramp is approximately double a frequency of the first ramp.

Abstract: A system includes a charge pump having an input coupled to a first voltage and an output at a second voltage, the second voltage greater than the first voltage. The system also includes an amplifier having a first input, a second input, and a third input, the first input coupled to the output of the charge pump, the second input coupled to the first voltage, the third input coupled to an input signal, the amplifier having an amplified output signal. The system also includes a maximum power detector coupled to the amplifier, the maximum power detector operable to determine whether the amplified output signal has reached a threshold output level and to reduce a power of the amplified output signal responsive to the determination.

Abstract: A device includes a first ramp generator having a first ramp generator output configured to provide a first ramp, a second ramp generator having a second ramp generator output configured to provide a second ramp, and a third ramp generator having a third ramp generator output configured to provide a third ramp. The first ramp is a sawtooth voltage waveform having a first common mode voltage and a first peak-to-peak voltage. The second ramp is a sawtooth voltage waveform having a second common mode voltage and a second peak-to-peak voltage. The third ramp is a sawtooth voltage waveform having a third common mode voltage and a third peak-to-peak voltage. A frequency of the second ramp is approximately equal to a frequency of the third ramp, and the frequency of the third ramp is approximately double a frequency of the first ramp.

Abstract: A power converter including a piezoelectric resonator. The power converter includes a first transistor coupled between an input terminal and a first plate of the piezoelectric resonator, and a second transistor coupled between the first plate of the piezoelectric resonator and an output terminal. A load may be coupled at the output terminal. Controller circuitry has inputs coupled to the input node, the output node, and to the first plate of the piezoelectric resonator, and outputs coupled to control terminals of the first and second transistors. The controller circuitry operates to turn on the first transistor responsive to a comparison of voltages at the first plate and the input terminal, turn on the second transistor responsive to a comparison of voltages at the first plate and the output terminal, and turn off one of the first and second transistors responsive to an output level at the output terminal.

Abstract: A device includes a first ramp generator having a first ramp generator output configured to provide a first ramp, a second ramp generator having a second ramp generator output configured to provide a second ramp, and a third ramp generator having a third ramp generator output configured to provide a third ramp. The first ramp is a sawtooth voltage waveform having a first common mode voltage and a first peak-to-peak voltage. The second ramp is a sawtooth voltage waveform having a second common mode voltage and a second peak-to-peak voltage. The third ramp is a sawtooth voltage waveform having a third common mode voltage and a third peak-to-peak voltage. A frequency of the second ramp is approximately equal to a frequency of the third ramp, and the frequency of the third ramp is approximately double a frequency of the first ramp.

Abstract: A multi-level ramp generator comprises three ramp generators. The first ramp generator generates a first ramp signal, comprising a sawtooth voltage waveform with a first common mode voltage and a first peak to peak voltage. The second ramp generator generates a second ramp signal, comprising a sawtooth voltage waveform with a second common mode voltage and a second peak-to-peak voltage. The third ramp generator generates a third ramp signal, comprising a sawtooth voltage waveform with a third common mode voltage and the second peak-to-peak voltage. The second and third ramp signals are in phase with each other and the first ramp signal is 180° out of phase with the second and third ramp signals. In some implementations, each of the first, second, and third ramp generators comprise a respective delay locked loop and a respective voltage controlled oscillator.

Abstract: An amplifier comprises eight transistors: the first coupled to a linked node and to a positive output node, the second coupled to the linked node and to a negative output node, the third coupled to the positive output node and a common potential, the fourth coupled to the negative output node and the common potential, the fifth coupled to a battery node, the sixth coupled to the fifth transistor and to the positive output node, the seventh coupled to the battery node, and the eighth coupled to the seventh transistor and to the negative output node. The amplifier also includes a charge pump to convert the battery voltage to an increased voltage on the linked node. The charge pump includes capacitors and operates at a lower frequency in lower power mode and a higher frequency in higher power mode to increase power provided to the linked node.

Abstract: Power converter circuitry includes a direct current (DC) input comprising a first DC input node and a second DC input node, an alternating current (AC) output comprising a first AC output node coupled to the first DC input node and a second AC output node, a first boost switch coupled between the second DC input node and a boost intermediate node, a second boost switch coupled between the boost intermediate node and a common node, a boost inductor coupled between the boost intermediate node and the first DC input node, a link capacitor coupled between the second DC input node and the common node, a first half-bridge switch coupled between the second DC input node and a half-bridge intermediate node, a second half-bridge switch coupled between the half-bridge intermediate node and the common node, and a half-bridge inductor coupled between the half-bridge intermediate node and the second AC output node.

Abstract: A multi-level ramp generator comprises three ramp generators. The first ramp generator generates a first ramp signal, comprising a sawtooth voltage waveform with a first common mode voltage and a first peak to peak voltage. The second ramp generator generates a second ramp signal, comprising a sawtooth voltage waveform with a second common mode voltage and a second peak-to-peak voltage. The third ramp generator generates a third ramp signal, comprising a sawtooth voltage waveform with a third common mode voltage and the second peak-to-peak voltage. The second and third ramp signals are in phase with each other and the first ramp signal is 180° out of phase with the second and third ramp signals. In some implementations, each of the first, second, and third ramp generators comprise a respective delay locked loop and a respective voltage controlled oscillator.

Abstract: An amplifier comprises eight transistors: the first coupled to a linked node and to a positive output node, the second coupled to the linked node and to a negative output node, the third coupled to the positive output node and a common potential, the fourth coupled to the negative output node and the common potential, the fifth coupled to a battery node, the sixth coupled to the fifth transistor and to the positive output node, the seventh coupled to the battery node, and the eighth coupled to the seventh transistor and to the negative output node. The amplifier also includes a charge pump to convert the battery voltage to an increased voltage on the linked node. The charge pump includes capacitors and operates at a lower frequency in lower power mode and a higher frequency in higher power mode to increase power provided to the linked node.

Abstract: Power converter circuitry includes a direct current (DC) input comprising a first DC input node and a second DC input node, an alternating current (AC) output comprising a first AC output node coupled to the first DC input node and a second AC output node, a first boost switch coupled between the second DC input node and a boost intermediate node, a second boost switch coupled between the boost intermediate node and a common node, a boost inductor coupled between the boost intermediate node and the first DC input node, a link capacitor coupled between the second DC input node and the common node, a first half-bridge switch coupled between the second DC input node and a half-bridge intermediate node, a second half-bridge switch coupled between the half-bridge intermediate node and the common node, and a half-bridge inductor coupled between the half-bridge intermediate node and the second AC output node.