Abstract: Apparatus and method are disclosed for implementing a clock and data recovery circuit for use on digital networks. A fully integrated phase-locked loop extracts a clock signal embedded in a data stream. Two trimming digital-to-analog converters simultaneously bring the center frequency of a current controlled oscillator and the phase-locked loop closed loop bandwidth to desired values. A triple sampler captures jittering data and aligns them with the recovered clock. The input jitter tolerance for the method and apparatus is two to three times that of previously reported phase-locked loop based circuits.