Patents by Inventor Yiu Chun Tse
Yiu Chun Tse has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11748284Abstract: A system and method for efficiently arbitrating traffic on a bus. A computing system includes a fabric for routing traffic among one or more agents and one or more endpoints. The fabric includes multiple arbiters in an arbitration hierarchy. Arbiters store traffic in buffers with each buffer associated with a particular traffic type and a source of the traffic. Arbiters maintain a respective urgency counter for keeping track of a period of time traffic of a particular type is blocked by upstream arbiters. When the block is removed, the traffic of the particular type has priority for selection based on the urgency counter. When arbiters receive feedback from downstream arbiters or sources, the arbiters adjust selection priority accordingly. For example, changes in bandwidth requirement, low latency tolerance and active status cause adjustments in selection priority of stored requests.Type: GrantFiled: July 14, 2021Date of Patent: September 5, 2023Assignee: Apple Inc.Inventors: Nachiappan Chidambaram Nachiappan, Jaideep Dastidar, Yiu Chun Tse, Ripudaman Singh, Shawn Munetoshi Fukami, Benjamin K. Dodge, Vinodh R. Cuppu
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Publication number: 20210342282Abstract: A system and method for efficiently arbitrating traffic on a bus. A computing system includes a fabric for routing traffic among one or more agents and one or more endpoints. The fabric includes multiple arbiters in an arbitration hierarchy. Arbiters store traffic in buffers with each buffer associated with a particular traffic type and a source of the traffic. Arbiters maintain a respective urgency counter for keeping track of a period of time traffic of a particular type is blocked by upstream arbiters. When the block is removed, the traffic of the particular type has priority for selection based on the urgency counter. When arbiters receive feedback from downstream arbiters or sources, the arbiters adjust selection priority accordingly. For example, changes in bandwidth requirement, low latency tolerance and active status cause adjustments in selection priority of stored requests.Type: ApplicationFiled: July 14, 2021Publication date: November 4, 2021Inventors: Nachiappan Chidambaram Nachiappan, Jaideep Dastidar, Yiu Chun Tse, Ripudaman Singh, Shawn Munetoshi Fukami, Benjamin K. Dodge, Vinodh R. Cuppu
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Publication number: 20210319077Abstract: Embodiments relate to a denominator circuit that determines the number of valid elements of a data surface covered by a kernel depending on various locations of the kernel relative to the data surface. The denominator circuit includes a first circuit and a second circuit that have the same structure. The first circuit receives numbers representing different horizontal locations of a reference point in the kernel and generates a first matrix with first output elements corresponding to the different horizontal locations. The second circuit receives numbers representing different vertical locations of a reference point in the kernel and generates a second matrix with second output elements corresponding to the different vertical locations. A matrix multiplication of the first matrix and the second matrix is performed to obtain an array of valid elements covered by the kernel.Type: ApplicationFiled: April 14, 2020Publication date: October 14, 2021Inventors: Yiu Chun TSE, Ji Liang SONG, PONAN KUO
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Patent number: 11144615Abstract: Embodiments relate to a denominator circuit that determines the number of valid elements of a data surface covered by a kernel depending on various locations of the kernel relative to the data surface. The denominator circuit includes a first circuit and a second circuit that have the same structure. The first circuit receives numbers representing different horizontal locations of a reference point in the kernel and generates a first matrix with first output elements corresponding to the different horizontal locations. The second circuit receives numbers representing different vertical locations of a reference point in the kernel and generates a second matrix with second output elements corresponding to the different vertical locations. A matrix multiplication of the first matrix and the second matrix is performed to obtain an array of valid elements covered by the kernel.Type: GrantFiled: April 14, 2020Date of Patent: October 12, 2021Assignee: APPLE INC.Inventors: Yiu Chun Tse, Ji Liang Song, Ponan Kuo
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Patent number: 11093425Abstract: A system and method for efficiently arbitrating traffic on a bus. A computing system includes a fabric for routing traffic among one or more agents and one or more endpoints. The fabric includes multiple arbiters in an arbitration hierarchy. Arbiters store traffic in buffers with each buffer associated with a particular traffic type and a source of the traffic. Arbiters maintain a respective urgency counter for keeping track of a period of time traffic of a particular type is blocked by upstream arbiters. When the block is removed, the traffic of the particular type has priority for selection based on the urgency counter. When arbiters receive feedback from downstream arbiters or sources, the arbiters adjust selection priority accordingly. For example, changes in bandwidth requirement, low latency tolerance and active status cause adjustments in selection priority of stored requests.Type: GrantFiled: August 20, 2018Date of Patent: August 17, 2021Assignee: Apple Inc.Inventors: Nachiappan Chidambaram Nachiappan, Jaideep Dastidar, Yiu Chun Tse, Ripudaman Singh, Shawn Munetoshi Fukami, Benjamin K. Dodge, Vinodh R. Cuppu
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Patent number: 10963172Abstract: A system and method for efficiently allocating data storage to agents. A computing system includes an interconnect with intermediate buffers for storing transactions and corresponding payload data during transport between sources and destinations. A data storage limit is set on an amount of data storage corresponding to outstanding transactions for each of the multiple sources based on the initial buffer assignments. A number of outstanding transactions for each of the multiple sources is limited based on a corresponding data storage limit. If the rate of allocation of a given buffer assigned to a first source exceeds a threshold, then a second source is selected with available space exceeding a threshold in an assigned buffer. If it is determined the second source is not assigned to a buffer with a rate of allocation exceeding a threshold, then buffer storage is reassigned from the second source to the first source.Type: GrantFiled: August 9, 2018Date of Patent: March 30, 2021Assignee: Apple Inc.Inventors: Nachiappan Chidambaram Nachiappan, David L. Trawick, Yiu Chun Tse, Deniz Balkan, Hengsheng Geng, Shawn Munetoshi Fukami, Jaideep Dastidar, Benjamin K. Dodge, Vinodh R. Cuppu
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Patent number: 10649922Abstract: A system and method for efficiently scheduling requests. In various embodiments, a processor sends commands such as read requests and write requests to an arbiter. The arbiter reduces latencies between commands being sent to a communication fabric and corresponding data being sent to the fabric. When the arbiter selects a given request, the arbiter identifies a first subset of stored requests affected by the given request being selected. The arbiter adjusts one or more attributes of the first subset of requests based on the selection of the given request. In one example, the arbiter replaces a weight attribute with a value, such as a zero value, indicating the first subset of requests should not be selected. Therefore, during the next selection by the arbiter, only the requests in a second subset different from the first subset are candidates for selection.Type: GrantFiled: August 6, 2018Date of Patent: May 12, 2020Assignee: Apple Inc.Inventors: Shawn Munetoshi Fukami, Jaideep Dastidar, Yiu Chun Tse
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Publication number: 20200057737Abstract: A system and method for efficiently arbitrating traffic on a bus. A computing system includes a fabric for routing traffic among one or more agents and one or more endpoints. The fabric includes multiple arbiters in an arbitration hierarchy. Arbiters store traffic in buffers with each buffer associated with a particular traffic type and a source of the traffic. Arbiters maintain a respective urgency counter for keeping track of a period of time traffic of a particular type is blocked by upstream arbiters. When the block is removed, the traffic of the particular type has priority for selection based on the urgency counter. When arbiters receive feedback from downstream arbiters or sources, the arbiters adjust selection priority accordingly. For example, changes in bandwidth requirement, low latency tolerance and active status cause adjustments in selection priority of stored requests.Type: ApplicationFiled: August 20, 2018Publication date: February 20, 2020Inventors: Nachiappan Chidambaram Nachiappan, Jaideep Dastidar, Yiu Chun Tse, Ripudaman Singh, Shawn Munetoshi Fukami, Benjamin K. Dodge, Vinodh R. Cuppu
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Publication number: 20200050379Abstract: A system and method for efficiently allocating data storage to agents. A computing system includes an interconnect with intermediate buffers for storing transactions and corresponding payload data during transport between sources and destinations. A data storage limit is set on an amount of data storage corresponding to outstanding transactions for each of the multiple sources based on the initial buffer assignments. A number of outstanding transactions for each of the multiple sources is limited based on a corresponding data storage limit. If the rate of allocation of a given buffer assigned to a first source exceeds a threshold, then a second source is selected with available space exceeding a threshold in an assigned buffer. If it is determined the second source is not assigned to a buffer with a rate of allocation exceeding a threshold, then buffer storage is reassigned from the second source to the first source.Type: ApplicationFiled: August 9, 2018Publication date: February 13, 2020Inventors: Nachiappan Chidambaram Nachiappan, David L. Trawick, Yiu Chun Tse, Deniz Balkan, Hengsheng Geng, Shawn Munetoshi Fukami, Jaideep Dastidar, Benjamin K. Dodge, Vinodh R. Cuppu
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Publication number: 20200042469Abstract: A system and method for efficiently scheduling requests. In various embodiments, a processor sends commands such as read requests and write requests to an arbiter. The arbiter reduces latencies between commands being sent to a communication fabric and corresponding data being sent to the fabric. When the arbiter selects a given request, the arbiter identifies a first subset of stored requests affected by the given request being selected. The arbiter adjusts one or more attributes of the first subset of requests based on the selection of the given request. In one example, the arbiter replaces a weight attribute with a value, such as a zero value, indicating the first subset of requests should not be selected. Therefore, during the next selection by the arbiter, only the requests in a second subset different from the first subset are candidates for selection.Type: ApplicationFiled: August 6, 2018Publication date: February 6, 2020Inventors: Shawn Munetoshi Fukami, Jaideep Dastidar, Yiu Chun Tse
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Patent number: 10423558Abstract: A system and method for efficiently routing data in a communication fabric. A computing system includes a fabric for routing data among one or more agents and a memory controller for system memory. The fabric includes multiple hierarchical clusters with a split topology where the data links are physically separated from the control links. A given cluster receives a write command and associated write data, and stores them in respective buffers. The given cluster marks the write command as a candidate to be issued to the memory controller when it is determined the write data will arrive ahead of the write command at the memory controller after being issued. The given cluster prevents the write command from becoming a candidate to be issued when it is determined the write data may not arrive ahead of the write command at the memory controller.Type: GrantFiled: August 8, 2018Date of Patent: September 24, 2019Assignee: Apple Inc.Inventors: Shawn Munetoshi Fukami, Yiu Chun Tse, David L. Trawick, Hengsheng Geng, Jaideep Dastidar, Vinodh R. Cuppu, Deniz Balkan
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Patent number: 10255218Abstract: A system and method for efficiently bridging two communication protocols. In various embodiments, a computing system includes an interconnect for routing traffic among agents and endpoints. The agents use a first communication protocol and the endpoints use a second communication protocol that differs from the first protocol with regard to at least the ordering that is enforced between transactions. A bridge selects transactions of a first type and a second type used in the first protocol for processing based on the first protocol ordering while using acknowledgments used by the second protocol.Type: GrantFiled: June 25, 2018Date of Patent: April 9, 2019Assignee: Apple Inc.Inventors: Yiu Chun Tse, Deniz Balkan, Vinodh R. Cuppu, Shawn Munetoshi Fukami, Jaideep Dastidar, Hengsheng Geng
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Patent number: 8295292Abstract: In one embodiment, a reassign command is received for reassigning a first node identified by a first global identifier (GID) from a first context identified by a first context ID (CID) to a second context identified by a second CID, the first and second contexts representing first and second linked lists, respectively. A walk-the-chain (WTC) command having the first GID and the first CID is issued to a first linked list processor. The first linked list processor is configured to access one or more nodes of the first context in an attempt to dequeue the first node from the first context. An enqueue command having the first GID and the second CID is issued to a second linked list processor. The second linked list processor is configured to insert the first node to the second context. The first and second linked list processors are cascaded to form a pipeline.Type: GrantFiled: May 19, 2010Date of Patent: October 23, 2012Assignee: Telefonaktiebolaget L M Ericsson (Publ)Inventors: Alfred Yiu-Chun Tse, Edmund G. Chen
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Publication number: 20110286463Abstract: In one embodiment, a reassign command is received for reassigning a first node identified by a first global identifier (GID) from a first context identified by a first context ID (CID) to a second context identified by a second CID, the first and second contexts representing first and second linked lists, respectively. A walk-the-chain (WTC) command having the first GID and the first CID is issued to a first linked list processor. The first linked list processor is configured to access one or more nodes of the first context in an attempt to dequeue the first node from the first context. An enqueue command having the first GID and the second CID is issued to a second linked list processor. The second linked list processor is configured to insert the first node to the second context. The first and second linked list processors are cascaded to form a pipeline.Type: ApplicationFiled: May 19, 2010Publication date: November 24, 2011Applicant: TELEFONAKTIEBOLAGET L M ERICSSON (PUBL)Inventors: Alfred Yiu-Chun Tse, Edmund G. Chen