Abstract: A system and method to implement an integrated circuit design are described. The method includes obtaining a timing database of current timing slack values based on current cell selection, placement, and routing for a plurality of cycles defined by a plurality of cycle boundaries, each cycle representing devices between a corresponding pair of the plurality of cycle boundaries, identifying candidate cycle boundaries among the plurality of cycle boundaries for slack redistribution, every one of the candidate cycle boundaries being associated with a positive timing slack, and selecting redistribution cycle boundaries among the candidate cycle boundaries. A modified timing database is generated based on redistributing the positive timing slack associated with the redistribution cycle boundaries, and power recovery is performed using the modified timing database to reduce power at one of more of the redistribution cycle boundaries.

Abstract: A system and method to implement an integrated circuit design are described. The method includes obtaining a timing database of current timing slack values based on current cell selection, placement, and routing for a plurality of cycles defined by a plurality of cycle boundaries, each cycle representing devices between a corresponding pair of the plurality of cycle boundaries, identifying candidate cycle boundaries among the plurality of cycle boundaries for slack redistribution, every one of the candidate cycle boundaries being associated with a positive timing slack, and selecting redistribution cycle boundaries among the candidate cycle boundaries. A modified timing database is generated based on redistributing the positive timing slack associated with the redistribution cycle boundaries, and power recovery is performed using the modified timing database to reduce power at one of more of the redistribution cycle boundaries.

Abstract: A system and method to implement an integrated circuit design are described. The method includes obtaining a timing database of current timing slack values based on current cell selection, placement, and routing for a plurality of cycles defined by a plurality of cycle boundaries, each cycle representing devices between a corresponding pair of the plurality of cycle boundaries, identifying candidate cycle boundaries among the plurality of cycle boundaries for slack redistribution, every one of the candidate cycle boundaries being associated with a positive timing slack, and selecting redistribution cycle boundaries among the candidate cycle boundaries. A modified timing database is generated based on redistributing the positive timing slack associated with the redistribution cycle boundaries, and power recovery is performed using the modified timing database to reduce power at one of more of the redistribution cycle boundaries.

Abstract: A system and method to implement an integrated circuit design are described. The method includes obtaining a timing database of current timing slack values based on current cell selection, placement, and routing for a plurality of cycles defined by a plurality of cycle boundaries, each cycle representing devices between a corresponding pair of the plurality of cycle boundaries, identifying candidate cycle boundaries among the plurality of cycle boundaries for slack redistribution, every one of the candidate cycle boundaries being associated with a positive timing slack, and selecting redistribution cycle boundaries among the candidate cycle boundaries. A modified timing database is generated based on redistributing the positive timing slack associated with the redistribution cycle boundaries, and power recovery is performed using the modified timing database to reduce power at one of more of the redistribution cycle boundaries.

Abstract: Integrated circuit design uses a library of structured soft blocks (SSBs) composed of pre-defined sets of cells with their logic implementation and placement templates with their relative placement information. A compiler receives a circuit description which includes an instance of an SSB and unfolds the instance according to the placement template to generate a modified circuit description which includes the relative placement information. The placement of circuit objects is optimized while maintaining relative locations for cells of the SSB instance according to the relative placement information. The SSB may be hierarchical. Gate resizing of cells in the SSB instance may result in a change in its bounds. A timing optimization procedure for the modified circuit description may be carried out while hiding internal details of the SSB instance. For example, buffers may be inserted in nets external to the SSB instance while preventing insertion of buffers in any internal nets.

Abstract: Integrated circuit design uses a library of structured soft blocks (SSBs) composed of pre-defined sets of cells with their logic implementation and placement templates with their relative placement information. A compiler receives a circuit description which includes an instance of an SSB and unfolds the instance according to the placement template to generate a modified circuit description which includes the relative placement information. The placement of circuit objects is optimized while maintaining relative locations for cells of the SSB instance according to the relative placement information. The SSB may be hierarchical. Gate resizing of cells in the SSB instance may result in a change in its bounds. A timing optimization procedure for the modified circuit description may be carried out while hiding internal details of the SSB instance. For example, buffers may be inserted in nets external to the SSB instance while preventing insertion of buffers in any internal nets.

Abstract: Disclosed is a method of estimating interconnect wire parasitics in integrated circuits which includes obtaining a circuit layout having circuit components placed thereon including source input/output (I/O) pins and sink I/O pins, the circuit layout having a circuit hierarchy, bubbling up of the I/O pins until all I/O pins are on a same level of the circuit hierarchy, and then estimating interconnect segments to be employed in interconnecting at least some circuit components of the placed circuit components of the circuit layout. Also disclosed is a circuit design system and program storage device.

Abstract: Disclosed is a method of estimating interconnect wire parasitics in integrated circuits which includes obtaining a circuit layout having circuit components placed thereon including source input/output (I/O) pins and sink I/O pins, the circuit layout having a circuit hierarchy, bubbling up of the I/O pins until all I/O pins are on a same level of the circuit hierarchy, and then estimating interconnect segments to be employed in interconnecting at least some circuit components of the placed circuit components of the circuit layout. Also disclosed is a circuit design system and program storage device.

Abstract: A circuit design technique is provided for automatically estimating lengths of interconnect segments to be employed in interconnecting at least some circuit components of a plurality of placed circuit components of a circuit layout. The automatically estimating includes automatically generating pin locations for a plurality of pins in at least one level of the hierarchy to be employed with the at least some circuit components of the circuit layout, wherein the interconnect segments interconnect the plurality of pins. A route estimator is employed to estimate lengths of the interconnect segments based on the pin locations of the plurality of pins. The estimated interconnect segment lengths are then employed in automatically estimating resistance capacitance interconnect parasitics for the interconnect segments to be employed in the circuit layout.

Abstract: A circuit design technique is provided for automatically estimating lengths of interconnect segments to be employed in interconnecting at least some circuit components of a plurality of placed circuit components of a circuit layout. The automatically estimating includes automatically generating pin locations for a plurality of pins in at least one level of the hierarchy to be employed with the at least some circuit components of the circuit layout, wherein the interconnect segments interconnect the plurality of pins. A route estimator is employed to estimate lengths of the interconnect segments based on the pin locations of the plurality of pins. The estimated interconnect segment lengths are then employed in automatically estimating resistance capacitance interconnect parasitics for the interconnect segments to be employed in the circuit layout.

Abstract: A physical device layout tool and method. The method and tool receive a user provided schematic with circuit data and placement parameters, including defaults. Further inputs include a definition of cell physical position in the horizontal direction, a definition of the cell's vertical stacking level, a definition of the cell orientation, a specification of vertical alignment of multiple cell instances, and a definition of vertical spacing between 2 adjacent cell instances. These input parameters are used to generate a layout with the placed circuit elements.

Abstract: A method for making a processor system immune to circuit failure caused by external noise using mirrored processors, and a recovery unit integral with the method, are disclosed. Identical addresses and data information is generated in each of two processors. The data is then partitioned into registers and Error Correction Codes (ECC's) are generated for the data. The address, data, and ECC information for each processor is then interlaced in a data structure. The interlaced structures of each processor are then compared. If the comparison yields no errors, the data is checkpointed in the recovery unit; if an error is detected, a recovery sequence can be initiated after the check-stop operation, whereby the system is restored to the last error-free checkpointing operation.