Abstract: A heuristic based motion estimation system and method for video compression may include: defining the target block 70; defining a simplified signature block 72; searching the reference frame using the simplified signature block 74; searching for the best match in the area centered around the location of the target block in the reference frame using the simplified signature 76; computing the sum of the absolute pixel-by-pixel difference using motion vectors of the target block's neighbors and a zero motion vector 78; selecting a new block with a motion vector with the minimum sum of the absolute pixel-by-pixel difference 80; and searching adjacent neighbors of the new block for minimum absolute difference match 82.

Abstract: A method of and circuitry for removing noise artifacts in decompressed video signals. A group of pixels is selected from a larger matrix of pixels from adjacent rows and columns of the matrix. A plurality of different subgroups of the group of pixels is selected, each subgroup including the same centrally located pixel. The maximum energy intensity difference emanating from each pixel in each of the subgroups is measured and the maximum difference among the pixels in each subgroup is determined. The subgroup having the lowest maximum difference is selected and the weighed mean of the selected pixels in the subgroup is computed with weights chosen to provide more significance to pixels which are located closer to the centrally located pixel. The centrally located pixel is then filtered with a linear filter, the coefficients of which are determined by the sum of absolute differences between the weighed mean and the pixels in the subgroup.

Abstract: A method (FIG. 1) of macroblock bit allocation in an MPEG picture encoding which assigns quantization facators according to macroblock quanfization noise immunity and subsequently adjusts quantization factors according to picture level total encoded bit target. Further reassignment of macroblock bits from high PSNR to low PSNR macroblocks.

Abstract: A pipelined Fast Fourier Transform (FFT) architecture includes a memory for storing complex number data. A pipelined data path is coupled to the memory for accessing R complex number data therefrom, for computing an FFT butterfly, and storing R results from the FFT butterfly computation in the memory during one pipeline cycle.

Abstract: A method for densely packing a complex multiplier for multiplying two complex numbers in the form of (A+jB) and (X+jY) is provided. The complex multiplier consist of two multipliers which perform (A*X), (A*Y), (B*X) and (B*Y) multiplications, and each multiplier has a plurality of partial product generating stages and a partial product summing stage. The method comprises interleaving the plurality of partial product generating stages of the (A*Y) multiplier between the plurality of partial product generating stages of the (A*X) multiplier, forming the partial product summing stage adjacent the interleaved partial product generating stages of the (A*X) and (A*Y) multipliers. Further interleave the plurality of partial product generating stages of the (B*Y) multiplier between the plurality of partial product generating stages of the (B*X) multiplier, and form the partial product summing stage adjacent the interleaved partial product gneerating stages of the (B*X) and (B*Y) multipliers.

Abstract: Apparatus for generating memory addresses for accessing and storing data in an FFT (Fast Fourier Transform) computation is provided. The FFT computation is typically performed by computing a plurality of FFT butterflies belonging to a plurality of ranks. The apparatus includes a butterfly counter for determining the current FFT butterfly being computed. The butterfly counter produces a plurality of butterfly carries. A rank counter for determining the rank of said current FFT butterfly being computed produces a rank number. Coupled to the rank and butterfly counters is incremental curcuitry, which generates an incremental number in response to the rank number and the butterfly carries. An adder circuitry coupled to the incremental circuitry adds the incremental number and a plurality of memory addresses to produce the FFT data memory addresses.