Abstract: An equalization circuit may include a buffer configured to sense an input signal according to a reference voltage. The equalization circuit may include a reference voltage generator configured to generate the reference voltage. The reference voltage may be changed in conformity with noise of the input signal.

Abstract: A duty-cycle correction circuit may include a delayed clock generation unit suitable for generating a plurality of delayed clocks by delaying a target clock by different delay values, an up/down signal generation unit suitable for selecting a delayed clock having a delay value corresponding to a first section of the target clock, and generating an up/down signal according to the lengths of a second section of the target clock and the first section of the selected delayed clock, a duty-cycle control code generation unit suitable for generating a duty-cycle control code in response to the up/down signal, a duty-cycle adjusting unit suitable for generating a duty-cycle correction clock by adjusting the duty-cycle of a source clock, and a control unit suitable for enabling the delayed clock generation unit during a duty-cycle correction period, and disabling the delayed clock generation unit during periods except for the duty-cycle correction period.

Abstract: An impedance calibration circuit may be provided. The impedance calibration circuit may include an adjusting circuit. The adjusting circuit may be configured to generate a calibration code based on a variation voltage, which may be applied to a calibration node coupled to a calibration pad, and a reference voltage. The adjusting circuit may be configured to apply a voltage, which may be generated according to a control signal generated based on an operational voltage mode in accordance with the calibration code, to the calibration node. The adjusting circuit may include a plurality of leg circuits. At least one of the leg circuits may include a plurality of legs configured to be selectively coupled to the calibration node based on the control signal.

Abstract: An impedance calibration circuit includes a first detection unit configured to generate a first pull-up impedance detection signal according to a resistance value of an internal reference resistor, a second detection unit configured to generate a second pull-up impedance detection signal according to a resistance value of an external reference resistor coupled to an external reference resistor pad, a switching unit configured to select the first pull-up impedance detection signal or the second pull-up impedance detection signal according to the internal impedance calibration enable signal and output the selected pull-up impedance detection signal, and an impedance calibration signal generation unit configured to generate a plurality of impedance calibration signals according to an output of the switching unit.

Abstract: A duty-cycle correction circuit may include a delayed clock generation unit suitable for generating a plurality of delayed clocks by delaying a target clock by different delay values, an up/down signal generation unit suitable for selecting a delayed clock having a delay value corresponding to a first section of the target clock, and generating an up/down signal according to the lengths of a second section of the target clock and the first section of the selected delayed clock, a duty-cycle control code generation unit suitable for generating a duty-cycle control code in response to the up/down signal, a duty-cycle adjusting unit suitable for generating a duty-cycle correction clock by adjusting the duty-cycle of a source clock, and a control unit suitable for enabling the delayed clock generation unit during a duty-cycle correction period, and disabling the delayed clock generation unit during periods except for the duty-cycle correction period.

Abstract: An impedance calibration circuit may be provided. The impedance calibration circuit may include an adjusting circuit. The adjusting circuit may be configured to generate a calibration code based on a variation voltage, which may be applied to a calibration node coupled to a calibration pad, and a reference voltage. The adjusting circuit may be configured to apply a voltage, which may be generated according to a control signal generated based on an operational voltage mode in accordance with the calibration code, to the calibration node. The adjusting circuit may include a plurality of leg circuits. At least one of the leg circuits may include a plurality of legs configured to be selectively coupled to the calibration node based on the control signal.

Abstract: An impedance calibration circuit includes a first detection unit configured to generate a first pull-up impedance detection signal according to a resistance value of an internal reference resistor, a second detection unit configured to generate a second pull-up impedance detection signal according to a resistance value of an external reference resistor coupled to an external reference resistor pad, a switching unit configured to select the first pull-up impedance detection signal or the second pull-up impedance detection signal according to the internal impedance calibration enable signal and output the selected pull-up impedance detection signal, and an impedance calibration signal generation unit configured to generate a plurality of impedance calibration signals according to an output of the switching unit.

Abstract: An impedance calibration circuit includes a first detection unit configured to generate a first pull-up impedance detection signal according to a resistance value of an internal reference resistor, a second detection unit configured to generate a second pull-up impedance detection signal according to a resistance value of an external reference resistor coupled to an external reference resistor pad, a switching unit configured to select the first pull-up impedance detection signal or the second pull-up impedance detection signal according to the internal impedance calibration enable signal and output the selected pull-up impedance detection signal, and an impedance calibration signal generation unit configured to generate a plurality of impedance calibration signals according to an output of the switching unit.

Abstract: An analog to digital converter includes a first DAC unit configured to vary a level of a reference voltage output through a first node according to a first code, a second DAC unit coupled in parallel to the first DAC unit on the basis of the first node and configured to vary the level of the reference voltage according to a second code, a comparator configured to generate a comparison result signal by comparing an input voltage and the reference voltage, and at least one register array configured to store the first code and the second code with initial values and store the first code and the second code by varying values of the first code and the second code according to the comparison result signal.

Abstract: An equalization circuit may include a buffer configured to sense an input signal according to a reference voltage. The equalization circuit may include a reference voltage generator configured to generate the reference voltage. The reference voltage may be changed in conformity with noise of the input signal.

Abstract: An equalization circuit may include a buffer configured to sense an input signal according to a reference voltage. The equalization circuit may include a reference voltage generator configured to generate the reference voltage. The reference voltage may be changed in conformity with noise of the input signal.

Abstract: An equalization circuit may include a buffer configured to sense an input signal according to a reference voltage. The equalization circuit may include a reference voltage generator configured to generate the reference voltage. The reference voltage may be changed in conformity with noise of the input signal.

Abstract: A duty cycle correction circuit may include: a phase mixing section capable of mixing a first integrated signal generated by integrating a positive clock signal, with a first compensation signal generated by differentiating and integrating the positive clock signal and a negative clock signal, respectively, to generate a first phase-mixed signal, and mixing a second integrated signal generated by integrating the negative clock signal, with a second compensation signal generated by integrating and differentiating the positive clock signal and the negative clock signal, respectively, to generate a second phase-mixed signal; and a noise removal section capable of receiving and removing a common mode noise between the first phase-mixed signal and the second phase-mixed signal by adjusting a cross-point therebetween, and outputting first and second duty-corrected clock signals.

Abstract: A duty cycle correction circuit may include: a phase mixing section capable of mixing a first integrated signal generated by integrating a positive clock signal, with a first compensation signal generated by differentiating and integrating the positive clock signal and a negative clock signal, respectively, to generate a first phase-mixed signal, and mixing a second integrated signal generated by integrating the negative clock signal, with a second compensation signal generated by integrating and differentiating the positive clock signal and the negative clock signal, respectively, to generate a second phase-mixed signal; and a noise removal section capable of receiving and removing a common mode noise between the first phase-mixed signal and the second phase-mixed signal by adjusting a cross-point therebetween, and outputting first and second duty-corrected clock signals.

Abstract: An equalization circuit may include a buffer configured to sense an input signal according to a reference voltage. The equalization circuit may include a reference voltage generator configured to generate the reference voltage. The reference voltage may be changed in conformity with noise of the input signal.

Abstract: Disclosed are a semiconductor memory device and an operation method thereof. The semiconductor memory device includes a main buffer suitable for storing input data during a first operation period of a write operation, a repair operation unit suitable for selectively latching the input data based on whether the input data is used for repair during the first operation period of the write operation; a repair buffer suitable for storing the latched input data during a second operation period subsequent to the first operation period, and a column operation unit suitable for controlling an operation to write the input data stored in the main buffer or the repair buffer in a main memory cell or a repair memory cell during the second operation period of the write operation.

Abstract: A semiconductor memory apparatus may include a memory cell array. The semiconductor memory apparatus may include an impedance calibration circuit configured to perform an impedance matching operation by generating an impedance code based on a voltage of an interface node determined by an external reference resistor or an internal reference resistor unit according to whether or not to the external reference resistor is coupled to the impedance calibration circuit. The semiconductor memory apparatus may include a data input/output (I/O) driver configured to receive input data from the memory cell array and generate output data in response to the impedance code.

Abstract: Disclosed are a semiconductor memory device and an operation method thereof. The semiconductor memory device includes a main buffer suitable for storing input data during a first operation period of a write operation, a repair operation unit suitable for selectively latching the input data based on whether the input data is used for repair during the first operation period of the write operation; a repair buffer suitable for storing the latched input data during a second operation period subsequent to the first operation period, and a column operation unit suitable for controlling an operation to write the input data stored in the main buffer or the repair buffer in a main memory cell or a repair memory cell during the second operation period of the write operation.

Abstract: A multiband antenna system installed onto a circuit board of a mobile device is provided. The antenna system includes a planar dielectric substrate, an upper conductor formed on an upper surface of the dielectric substrate and shaped as a coplanar wave guide and includes first and second ground parts and a radiator, and a lower conductor formed on the lower surface of the dielectric substrate and shaped as a coplanar wave guide and includes third and fourth ground parts and an electrode part, via-holes that pass through the dielectric substrate and are electrically connected to the first ground part to the third, the second ground part to the fourth, and the radiator to the electrode part, respectively, and solder balls connect the electrode part to an electric wire of the circuit board and also the third and fourth ground parts to the ground of the circuit board.