Patents by Inventor Yo-Sep LEE
Yo-Sep LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11804258Abstract: A semiconductor memory apparatus includes a first memory cell array, a second memory cell array, and a hammering control circuit. The first memory cell array includes a first row hammer memory cell. The second memory cell array includes a second row hammer memory cell. The hammering control circuit controls the number of active operations on a first word line to be stored in the second row hammer memory cell and controls the number of active operations on a second word line to be stored in the first row hammer memory cell.Type: GrantFiled: December 10, 2021Date of Patent: October 31, 2023Assignee: SK hynix Inc.Inventor: Yo Sep Lee
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Patent number: 11599306Abstract: A memory device includes a data storage circuit configured to access a cell array having first data stored therein when an arithmetic active operation is performed, output the first data when a first read operation is performed, access a cell array having second data stored therein when an active operation is performed, and output the second data when a second read operation is performed. The memory device also includes an arithmetic circuit configured to receive latch data generated through the first read operation and read data generated through the second read operation, and perform an arithmetic operation on the latch data and the read data.Type: GrantFiled: May 24, 2021Date of Patent: March 7, 2023Assignee: SK hynix Inc.Inventor: Yo Sep Lee
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Publication number: 20230040958Abstract: A semiconductor memory apparatus includes a first memory cell array, a second memory cell array, and a hammering control circuit. The first memory cell array includes a first row hammer memory cell. The second memory cell array includes a second row hammer memory cell. The hammering control circuit controls the number of active operations on a first word line to be stored in the second row hammer memory cell and controls the number of active operations on a second word line to be stored in the first row hammer memory cell.Type: ApplicationFiled: December 10, 2021Publication date: February 9, 2023Applicant: SK hynix Inc.Inventor: Yo Sep LEE
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Publication number: 20220375900Abstract: A stacked semiconductor device includes a plurality of stacked semiconductor dies electrically connected with each other, a first power line electrically connected to a lowermost semiconductor die among the stacked semiconductor dies, a second power line formed over an uppermost semiconductor die among the stacked semiconductor dies, and an external connection line electrically connecting the first power line and the second power line.Type: ApplicationFiled: December 10, 2021Publication date: November 24, 2022Applicant: SK hynix Inc.Inventor: Yo Sep LEE
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Publication number: 20220244889Abstract: A memory device includes a data storage circuit configured to access a cell array having first data stored therein when an arithmetic active operation is performed, output the first data when a first read operation is performed, access a cell array having second data stored therein when an active operation is performed, and output the second data when a second read operation is performed. The memory device also includes an arithmetic circuit configured to receive latch data generated through the first read operation and read data generated through the second read operation, and perform an arithmetic operation on the latch data and the read data.Type: ApplicationFiled: May 24, 2021Publication date: August 4, 2022Applicant: SK hynix Inc.Inventor: Yo Sep LEE
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Patent number: 11289174Abstract: A stacked semiconductor device including a plurality of semiconductor chips that are stacked and transfer signals through a plurality of through-electrodes, wherein at least one of the semiconductor chips comprises a first clock generation circuit suitable for generating first and second test clocks by dividing or buffering an external clock according to an operating information signal for indicating a high-speed test operation and a low-speed test operation; a first latch circuit suitable for latching a test control signal according to the first and second test clocks to generate first and second latched signals; and an input signal control circuit suitable for generating first and second internal control signals by re-latching the second latched signal according to the first test clock, and re-latching the first latched signal according to the second test clock.Type: GrantFiled: April 15, 2020Date of Patent: March 29, 2022Assignee: SK hynix Inc.Inventors: Yo-Sep Lee, Dong-Ha Lee, Seon-Woo Hwang
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Patent number: 11222684Abstract: A refresh control device, and a memory device may be provided. The latch controller may include a first oscillator configured to generate a first oscillation signal, and a second oscillator configured to generate a second oscillation signal. The latch controller may be configured to receive a precharge signal and prevent the second oscillation signal from being synchronized with the precharge signal.Type: GrantFiled: November 26, 2019Date of Patent: January 11, 2022Assignee: SK hynix Inc.Inventors: Jae Seung Lee, Chang Hyun Kim, Yo Sep Lee
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Patent number: 11139041Abstract: A stacked semiconductor device includes semiconductor chips, each including a signal transfer circuit respectively transferring a command, an address, and a chip select signal to first to third through electrodes, and respectively transferring a test address and a chip ID to the second and third through electrodes according to a test control signal; a command reception circuit transferring a test command or a signal transferred from the first through electrode to an internal circuit when a signal transferred from the third through electrode is identical to the chip ID coincide with each other; and a test control circuit activating the test control signal according to deactivation of a test control signal of an upper chip, and generating the test command and the test address according to the test control signal.Type: GrantFiled: October 30, 2019Date of Patent: October 5, 2021Assignee: SK hynix Inc.Inventor: Yo-Sep Lee
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Publication number: 20210193253Abstract: A stacked semiconductor device including a plurality of semiconductor chips that are stacked and transfer signals through a plurality of through-electrodes, wherein at least one of the semiconductor chips comprises a first clock generation circuit suitable for generating first and second test clocks by dividing or buffering an external clock according to an operating information signal for indicating a high-speed test operation and a low-speed test operation; a first latch circuit suitable for latching a test control signal according to the first and second test clocks to generate first and second latched signals; and an input signal control circuit suitable for generating first and second internal control signals by re-latching the second latched signal according to the first test clock, and re-latching the first latched signal according to the second test clock.Type: ApplicationFiled: April 15, 2020Publication date: June 24, 2021Inventors: Yo-Sep LEE, Dong-Ha LEE, Seon-Woo HWANG
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Patent number: 10867656Abstract: A memory includes: first to Nth areas refreshed based on first to Nth refresh control signals, respectively; a control signal generation circuit suitable for generating the second to Nth refresh control signals by sequentially delaying the first refresh control signal, and generating the first refresh control signal by delaying the Nth refresh control signal; an address counter suitable for changing a refresh address, corresponding to each round for activations of the first to Nth refresh control signals, based on the Nth refresh control signal; and a refresh stop circuit suitable for stopping a refresh operation when the round is repeated by a predetermined number.Type: GrantFiled: May 31, 2019Date of Patent: December 15, 2020Assignee: SK hynix Inc.Inventor: Yo-Sep Lee
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Publication number: 20200303030Abstract: A stacked semiconductor device includes semiconductor chips, each including a signal transfer circuit respectively transferring a command, an address, and a chip select signal to first to third through electrodes, and respectively transferring a test address and a chip ID to the second and third through electrodes according to a test control signal; a command reception circuit transferring a test command or a signal transferred from the first through electrode to an internal circuit when a signal transferred from the third through electrode is identical to the chip ID coincide with each other; and a test control circuit activating the test control signal according to deactivation of a test control signal of an upper chip, and generating the test command and the test address according to the test control signal.Type: ApplicationFiled: October 30, 2019Publication date: September 24, 2020Inventor: Yo-Sep LEE
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Publication number: 20200098418Abstract: A refresh control device, and a memory device may be provided. The latch controller may include a first oscillator configured to generate a first oscillation signal, and a second oscillator configured to generate a second oscillation signal. The latch controller may be configured to receive a precharge signal and prevent the second oscillation signal from being synchronized with the precharge signal.Type: ApplicationFiled: November 26, 2019Publication date: March 26, 2020Applicant: SK hynix Inc.Inventors: Jae Seung LEE, Chang Hyun KIM, Yo Sep LEE
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Publication number: 20200090733Abstract: A memory includes: first to Nth areas refreshed based on first to Nth refresh control signals, respectively; a control signal generation circuit suitable for generating the second to Nth refresh control signals by sequentially delaying the first refresh control signal, and generating the first refresh control signal by delaying the Nth refresh control signal; an address counter suitable for changing a refresh address, corresponding to each round for activations of the first to Nth refresh control signals, based on the Nth refresh control signal; and a refresh stop circuit suitable for stopping a refresh operation when the round is repeated by a predetermined number.Type: ApplicationFiled: May 31, 2019Publication date: March 19, 2020Inventor: Yo-Sep LEE
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Patent number: 10529405Abstract: A refresh control device, and a memory device may be provided. The latch controller may include a first oscillator configured to generate a first oscillation signal, and a second oscillator configured to generate a second oscillation signal. The latch controller may be configured to receive a precharge signal and prevent the second oscillation signal from being synchronized with the precharge signal.Type: GrantFiled: May 10, 2018Date of Patent: January 7, 2020Assignee: SK hynix Inc.Inventors: Jae Seung Lee, Chang Hyun Kim, Yo Sep Lee
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Patent number: 10475486Abstract: An electronic device includes a pulse generator, a signal synthesizer, and a first storage circuit. The pulse generator generates a mode active pulse and a mode pre-charge pulse in response to an operation mode signal. The signal synthesizer synthesizes an active signal and the mode active pulse to generate a synthesized active signal. The signal synthesizer synthesizes a pre-charge signal and the mode pre-charge pulse to generate a synthesized pre-charge signal. The first storage circuit performs an active operation, a read operation, or a pre-charge operation in response to the synthesized active signal, a read signal, and the synthesized pre-charge signal in each of a first read mode and a second read mode.Type: GrantFiled: January 12, 2018Date of Patent: November 12, 2019Assignee: SK hynix Inc.Inventor: Yo Sep Lee
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Patent number: 10388336Abstract: A semiconductor apparatus includes a decoder configured to decode an internal command, and generate a first decoding command and a second decoding command. The semiconductor apparatus may include an output timing control circuit configured to delay the second decoding command by a predetermined cycle of the internal clock, and output a delayed decoding command. The semiconductor apparatus may include an input/output control latch circuit configured to output the internal address as a first latch address based on the second decoding command and the delayed decoding command. The semiconductor apparatus may include an input control latch circuit configured to output the internal address as a second latch address based on the first decoding command.Type: GrantFiled: April 5, 2019Date of Patent: August 20, 2019Assignee: SK hynix Inc.Inventor: Yo Sep Lee
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Publication number: 20190237115Abstract: A semiconductor apparatus includes a decoder configured to decode an internal command, and generate a first decoding command and a second decoding command. The semiconductor apparatus may include an output timing control circuit configured to delay the second decoding command by a predetermined cycle of the internal clock, and output a delayed decoding command. The semiconductor apparatus may include an input/output control latch circuit configured to output the internal address as a first latch address based on the to second decoding command and the delayed decoding command. The semiconductor apparatus may include an input control latch circuit configured to output the internal address as a second latch address based on the first decoding command.Type: ApplicationFiled: April 5, 2019Publication date: August 1, 2019Applicant: SK hynix Inc.Inventor: Yo Sep LEE
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Patent number: 10297293Abstract: A semiconductor apparatus includes a decoder configured to decode an internal command, and generate a first decoding command and a second decoding command. The semiconductor apparatus may include an output timing control circuit configured to delay the second decoding command by a predetermined cycle of the internal clock, and output a delayed decoding command. The semiconductor apparatus may include an input/output control latch circuit configured to output the internal address as a first latch address based on the second decoding command and the delayed decoding command. The semiconductor apparatus may include an input control latch circuit configured to output the internal address as a second latch address based on the first decoding command.Type: GrantFiled: March 14, 2017Date of Patent: May 21, 2019Assignee: SK hynix Inc.Inventor: Yo Sep Lee
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Publication number: 20190027198Abstract: An electronic device includes a pulse generator, a signal synthesizer, and a first storage circuit. The pulse generator generates a mode active pulse and a mode pre-charge pulse in response to an operation mode signal. The signal synthesizer synthesizes an active signal and the mode active pulse to generate a synthesized active signal. The signal synthesizer synthesizes a pre-charge signal and the mode pre-charge pulse to generate a synthesized pre-charge signal. The first storage circuit performs an active operation, a read operation, or a pre-charge operation in response to the synthesized active signal, a read signal, and the synthesized pre-charge signal in each of a first read mode and a second read mode.Type: ApplicationFiled: January 12, 2018Publication date: January 24, 2019Applicant: SK hynix Inc.Inventor: Yo Sep LEE
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Publication number: 20180261276Abstract: A refresh control device, and a memory device may be provided. The latch controller may include a first oscillator configured to generate a first oscillation signal, and a second oscillator configured to generate a second oscillation signal. The latch controller may be configured to receive a precharge signal and prevent the second oscillation signal from being synchronized with the precharge signal.Type: ApplicationFiled: May 10, 2018Publication date: September 13, 2018Applicant: SK hynix Inc.Inventors: Jae Seung LEE, Chang Hyun KIM, Yo Sep LEE