Abstract: An apparatus for providing a bias current to a hall sensor includes: a bias provider configured to provide the bias current to the hall sensor; and a processor configured to produce a bias current control value based on a node voltage between the hall sensor and the bias provider, wherein the bias provider is configured to vary the bias current based on the bias current control value.

Abstract: A slave device includes: a serial communications slave having an address designated for performing serial communications with a master; a single address determination pin configured to be, selectively, connected to a power terminal without being connected to a first external resistor, connected to a ground terminal without being connected through a second external resistor, connected to the power terminal through the first external resistor, or connected to the ground terminal through a second external resistor; and an address allocator configured to designate the address of the serial communications slave based on a plurality of state bits determined depending on a connection state of the single address determination pin.

Abstract: An analog-digital conversion apparatus includes: an analog-digital converter (ADC) included in an integrated circuit (IC) and configured to operate based on a sampling clock constituting a portion of a plurality of clocks; and a driver included in the IC and configured to operate based on another portion of the plurality of clocks, and produce a driving signal based on a digital value output from the ADC. The ADC and the driver are synchronized with each other based on an interrupt request (Irq) of the IC.

Abstract: An analog-digital conversion apparatus includes: an analog-digital converter (ADC) included in an integrated circuit (IC) and configured to operate based on a sampling clock constituting a portion of a plurality of clocks; and a driver included in the IC and configured to operate based on another portion of the plurality of clocks, and produce a driving signal based on a digital value output from the ADC. The ADC and the driver are synchronized with each other based on an interrupt request (Irq) of the IC.

Abstract: A slave device includes: a serial communications slave having an address designated for performing serial communications with a master; a single address determination pin configured to be, selectively, connected to a power terminal without being connected to a first external resistor, connected to a ground terminal without being connected through a second external resistor, connected to the power terminal through the first external resistor, or connected to the ground terminal through a second external resistor; and an address allocator configured to designate the address of the serial communications slave based on a plurality of state bits determined depending on a connection state of the single address determination pin.

Abstract: An apparatus with hall sensor common mode voltage adjustment includes: a bias provider configured to provide a bias current to the hall sensor; a first voltage regulator configured to vary a first voltage difference between the hall sensor and the bias provider, based on the bias current; and a second voltage regulator configured to vary a second voltage difference between the hall sensor and a ground, based on the bias current. The first and second voltage differences are variable such that a difference between the first voltage difference and the second voltage difference corresponds to a difference between a common mode voltage of first and second hall sensor output terminals of the hall sensor and a reference voltage.

Abstract: An apparatus for providing a bias current to a hall sensor includes: a bias provider configured to provide the bias current to the hall sensor; and a processor configured to produce a bias current control value based on a node voltage between the hall sensor and the bias provider, wherein the bias provider is configured to vary the bias current based on the bias current control value.

Abstract: A hall sensor device includes: an amplifier configured to amplify a detection signal of a hall sensor; and a current supplier configured to provide a compensation current to a feedback line of the amplifier according to an offset of the detection signal, to cancel the offset.

Abstract: A hall sensor device includes: an amplifier configured to amplify a detection signal of a hall sensor; and a current supplier configured to provide a compensation current to a feedback line of the amplifier according to an offset of the detection signal, to cancel the offset.

Abstract: There is provided a frequency correcting system including an oscillator outputting a target signal having an oscillating frequency, and a frequency corrector comparing the frequency of the target signal with the frequency of the reference signal and correcting the oscillating frequency to match a frequency of a predetermined reference signal, thereby automatically correcting an error in the oscillating frequency occurring during the manufacturing processes to provide precise and stable oscillating frequency.

Abstract: Embodiments of the invention provide a mold for forming a lens including a first core coupled with a first core hole of a first mold, and a second core coupled with a second core hole of a second mold to face the first core. In accordance with at least one embodiment, the first core and the second core are made of a material having a coefficient of thermal expansion larger than that of the first mold and the second mold, and outer diameters of the first core and the second core are each formed to be smaller than diameters of the first core hole and the second core hole.

Abstract: Provided is a metering device and a metering method. The metering device includes a Hall sensor configured to output a Hall voltage generated by a magnetic field generated from a power supply line, an analog-digital converter configured to receive a voltage signal between a minimum voltage value and a maximum voltage value to convert the voltage signal into a digital signal and output the digital signal, an output adjustment unit connected between the Hall sensor and the analog-digital converter, and configured to attenuate and output the Hall voltage when the Hall voltage output from the Hall sensor is larger than the maximum voltage value and output adjustment information that adjusted the Hall voltage, and a control unit connected to the analog-digital converter and the output adjustment unit, and calculate the digital signal output from the analog-digital converter and the adjustment information output from the output adjustment unit to calculate wattage.

Abstract: Disclosed herein are a clock generating circuit having a parasitic oscillation suppressing unit and a method of suppressing parasitic oscillation using the same. An output VDD of a parasitic component eliminating circuit is maintained in a high or low state according to the condition in which the output VDD falls from the high state to the low state and the condition in which the output VDD rises from the low state to the high state based on a threshold voltage VSPH when an input signal of the parasitic component eliminating circuit is changed from 0 to 1 and a threshold voltage VSPL when the input signal of the parasitic component eliminating circuit is changed from 1 to 0. Undesired parasitic oscillation is eliminated (suppressed) by the parasitic component eliminating circuit provided between a oscillator and a buffer.

Abstract: There are provided an apparatus and a method for measuring a temperature. The apparatus includes: a temperature sensor measuring a temperature and providing the measured temperature; a temperature comparing unit comparing the measured temperature with a preset reference temperature and providing a comparison result signal; a quartz oscillating unit generating an oscillating frequency signal according to temperature; a frequency counting unit counting a frequency of the oscillating frequency signal and providing a frequency count value; and a signal processing unit determining a temperature according to the comparison result signal and the frequency count value.

Abstract: Disclosed is an electronic watt-hour meter including: a plurality of sigma-delta modulators converting a plurality of analog detection currents, acquired by detecting currents flowing through a plurality of power lines having different phases, and a plurality of analog detection voltages, acquired by detecting voltages applied to the plurality of power lines, into respective bitstreams; a first register storing the bitstreams of the plurality of detection currents; a second register storing the bitstreams of the plurality of detection voltages; a register controller controlling the first register and the second register to sequentially output the bitstreams of the plurality of detection currents and the bitstreams of the plurality of detection voltages while simultaneously outputting bitstreams of detection currents and bitstreams of detection voltages detected in the same power line; a first decimation filter converting the bitstreams of the plurality of detection currents sequentially outputted from the fir

Abstract: An integrated tracking filter includes: an amplifying unit having first to third terminals, the first terminal being connected to an input stage and the second terminal being connected to an output stage, and amplifying a signal from the input stage; a loading unit connected between a power source stage and the second terminal of the amplifying unit; a current source connected between the third terminal of the amplifying unit and a ground; and a switched LC filter unit connected between the third terminal of the amplifying unit and the ground and varying a pass band of the signal.

Abstract: A mixer includes, an input current generation unit generating an input current; a first path circuit unit including n number of transistors having sources connected in common to an output node of the input current generation unit; and a second path circuit unit including n number of transistors having sources connected in common to the output node of the input current generation unit, and respectively corresponding to the n number of transistors included in the first path circuit unit. Local oscillator signals sequentially phase-shifted by 180°/n are individually input to gates of the n number of transistors included in the first path circuit unit, and local oscillator signals having opposite phases to the local oscillator signals input to the gates of the corresponding transistors included in the first path circuit unit are individually input to gates of the n number of transistors included in the second path circuit unit.

Abstract: A phase frequency detector for improving in-band phase noise characteristics of a PLL is disclosed. The phase frequency detector compares a reference frequency with a division frequency created by dividing an output frequency of a voltage controlled oscillator (VCO) by a predetermined division ratio, creates a phase-difference signal corresponding to a phase difference between the reference frequency and the division frequency, and improves noise characteristics.

Abstract: The invention relates to method of determining a fractional division ratio using a sigma-delta modulator. In this method, the fractional division ratio of the sigma-delta modulator is set as k/q, where k is an integer input value of the sigma-delta modulator, and q is a value preset to determine a predetermined frequency resolution. A spur generated from the voltage controller oscillator according to the variation of k is measured while the value k is varied. When the spur takes place at a certain value of k where a frequency is lower than a predetermined reference frequency, the fractional division ratio is reset as k/(q+1) or k/(q?1) for the certain value of k. The reset fractional division ratio is provided to the divider.

Abstract: The invention provides a low divide ratio programmable frequency divider of a fractional-N type applied to a digital MOPLL tuner and a method thereof. In the invention, a divide ratio assigner assigns divide data as a main divide ratio and a pulse swallow value according to a first or a second dividing operation mode in response to a mode selection signal. A prescaler operates on the first or second divide operation mode in response to the mode selection signal. Also, a main counter divides a frequency from the prescaler by the main divide ratio. Further, a pulse swallow counter counts a clock of the main counter while outputting a pulse swallow signal to the prescaler. The pulse swallow signal has a swallow level if a counting value corresponds to the pulse swallow value, and a non-swallow level if the counting value does not correspond to the pulse swallow value.