Patents by Inventor Yoann Guillemenet
Yoann Guillemenet has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9368204Abstract: The invention concerns a memory device comprising at least one memory cell comprising: a first transistor (102) coupled between a first storage node (106) and a first resistance switching element (202) programmed to have a first resistance; and a second transistor (104) coupled between a second storage node (108) and a second resistance switching element (204) programmed to have a second resistance, a control terminal of said first transistor being coupled to said second storage node, and a control terminal of said second transistor being coupled to said first storage node; and control circuitry (602) adapted to store a data value (DNV) at said first and second storage nodes by coupling said first and second storage nodes to a first supply voltage (VDD, GND), the data value being determined by the relative resistances of the first and second resistance switching elements.Type: GrantFiled: January 19, 2012Date of Patent: June 14, 2016Assignee: Centre National de la Recherche Scientifique Universite Montpellier 2Inventors: Yoann Guillemenet, Lionel Torres, Guillaume Prenat, Kholdoun Torki, Gregory Di Pendina
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Patent number: 9224463Abstract: A memory device includes at least one memory cell having a first transistor coupled between a first storage node and a first supply voltage; a second transistor coupled between a second storage node and the first supply voltage and a single resistance switching element. Control terminals of the first and second transistors are coupled to the second and first storage nodes respectively. The single resistive switching element is coupled in series with the first transistor and is programmable to have one of first and second resistances. The first storage node is coupled to a first access line via a third transistor connected to said first storage node, and the second storage node is coupled to a second access line via a fourth transistor connected to the second storage node.Type: GrantFiled: January 19, 2012Date of Patent: December 29, 2015Assignees: Centre National de la Recherche Scientifique, Université Montpellier 2Inventors: Yoann Guillemenet, Lionel Torres
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Patent number: 9117521Abstract: The invention concerns a non-volatile memory element comprising: first and second transistors (106, 108) forming an inverter (104) coupled between a first storage node (112) and an output (110) of the memory element; a third transistor (116) coupled between the first storage node (112) and a first supply voltage (GND, VDD) and comprising a control terminal coupled to said output; a first resistance switching element (102) coupled in series with said third transistor and programmed to have one of first and second resistances (Rmin, Rmax) representing a non-volatile data bit; a fourth transistor (118) coupled between said storage node (112) a second supply voltage (VDD, GND); and control circuitry (130) adapted to activate said third transistor at the start of a transfer phase of said non-volatile data bit to said storage node, and to control said fourth transistor to couple said storage node to said second supply voltage during said transfer phase.Type: GrantFiled: June 14, 2012Date of Patent: August 25, 2015Assignees: Centre National de la Recherche Scientifique, Université Montpellier 2Inventors: Yoann Guillemenet, Lionel Torres
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Patent number: 9053782Abstract: The invention concerns a memory device comprising at least one memory cell comprising: first and second pairs of cross-coupled transistors; and a first resistance switching element (202) coupled between a first supply voltage (VDD, GND) and a first transistor of said first pair of transistors and programmed to have one of first and second resistances; and control circuitry adapted to store a data value (DNV) at said first and second storage nodes by coupling said first storage node to said second supply voltage (VDD, GND), the data value being determined by the programmed resistance of the first resistance switching element.Type: GrantFiled: June 14, 2012Date of Patent: June 9, 2015Assignees: Centre National de la Recherche Scientifique, Universite Montpellier 2Inventors: Yoann Guillemenet, Lionel Torres
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Patent number: 9042157Abstract: The invention concerns a memory device comprising at least one memory cell comprising: a first transistor (102) coupled between a first storage node (106) and a first supply line (GND, VDD); a second transistor (104) coupled between a second storage node and said first supply line (GND, VDD), control terminals of said first and second transistors being coupled to said second and first storage nodes respectively; a third transistor (110) coupled between said first storage node and a first access line (BL) and controllable via a first control line (WL1); a fourth transistor (112, 712) coupled between said second storage node (108) and a second access line (BLB) and controllable via a second control line; and a first resistance switching element (202) coupled in series with said first transistor and programmable to have one of first and second resistive states.Type: GrantFiled: January 19, 2012Date of Patent: May 26, 2015Assignees: CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE, UNIVERSITE MONTPELLIER 2Inventors: Yoann Guillemenet, Lionel Torres
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Publication number: 20140269003Abstract: The invention concerns a non-volatile memory element comprising: first and second transistors (106, 108) forming an inverter (104) coupled between a first storage node (112) and an output (110) of the memory element; a third transistor (116) coupled between the first storage node (112) and a first supply voltage (GND, VDD) and comprising a control terminal coupled to said output; a first resistance switching element (102) coupled in series with said third transistor and programmed to have one of first and second resistances (Rmin, Rmax) representing a non-volatile data bit; a fourth transistor (118) coupled between said storage node (112) a second supply voltage (VDD, GND); and control circuitry (130) adapted to activate said third transistor at the start of a transfer phase of said non-volatile data bit to said storage node, and to control said fourth transistor to couple said storage node to said second supply voltage during said transfer phase.Type: ApplicationFiled: June 14, 2012Publication date: September 18, 2014Applicants: Universite Montpellier 2, Centre National de la Recherche ScientifiqueInventors: Yoann Guillemenet, Lionel Torres
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Publication number: 20140167816Abstract: The invention concerns a memory device comprising at least one memory cell comprising: first and second pairs of cross-coupled transistors; and a first resistance switching element (202) coupled between a first supply voltage (VDD, GND) and a first transistor of said first pair of transistors and programmed to have one of first and second resistances; and control circuitry adapted to store a data value (DNV) at said first and second storage nodes by coupling said first storage node to said second supply voltage (VDD, GND), the data value being determined by the programmed resistance of the first resistance switching element.Type: ApplicationFiled: June 14, 2012Publication date: June 19, 2014Applicants: UNIVERSITE MONTPELLIER 2, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUEInventors: Yoann Guillemenet, Lionel Torres
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Publication number: 20140070844Abstract: The invention concerns a memory device comprising at least one memory cell comprising: a first transistor (102) coupled between a first storage node (106) and a first resistance switching element (202) programmed to have a first resistance; and a second transistor (104) coupled between a second storage node (108) and a second resistance switching element (204) programmed to have a second resistance, a control terminal of said first transistor being coupled to said second storage node, and a control terminal of said second transistor being coupled to said first storage node; and control circuitry (602) adapted to store a data value (DNV) at said first and second storage nodes by coupling said first and second storage nodes to a first supply voltage (VDD, GND), the data value being determined by the relative resistances of the first and second resistance switching elements.Type: ApplicationFiled: January 19, 2012Publication date: March 13, 2014Applicants: UNIVERSITE MONTPELLIER 2, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUEInventors: Yoann Guillemenet, Lionel Torres, Guillaume Prenat, Kholdoun Torki, Gregory Di Pendina
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Publication number: 20140050012Abstract: The invention concerns a memory device comprising at least one memory cell comprising: a first transistor (102) coupled between a first storage node (106) and a first supply line (GND, VDD); a second transistor (104) coupled between a second storage node and said first supply line (GND, VDD), control terminals of said first and second transistors being coupled to said second and first storage nodes respectively; a third transistor (110) coupled between said first storage node and a first access line (BL) and controllable via a first control line (WL1); a fourth transistor (112, 712) coupled between said second storage node (108) and a second access line (BLB) and controllable via a second control line; and a first resistance switching element (202) coupled in series with said first transistor and programmable to have one of first and second resistive states.Type: ApplicationFiled: January 19, 2012Publication date: February 20, 2014Applicants: UNIVERSITE MONTPELLIER 2, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUEInventors: Yoann Guillemenet, Lionel Torres
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Publication number: 20140043062Abstract: The invention concerns a memory device comprising at least one memory cell comprising: a first transistor (102) coupled between a first storage node (106) and a first supply voltage (GND, VDD); a second transistor (104) coupled between a second storage node (108) and said first supply voltage, control terminals of the first and second transistors being coupled to the second and first storage nodes respectively; and a single resistance switching element (202), wherein said single resistive switching element is coupled in series with said first transistor and is programmable to have one of first and second resistances (Rmin, Rmax), wherein said first storage node is coupled to a first access line (BL) via a third transistor (110, 810) connected to said first storage node, and said second storage node is coupled to a second access line (BLB) via a fourth transistor (112, 812) connected to said second storage node.Type: ApplicationFiled: January 19, 2012Publication date: February 13, 2014Applicants: UNIVERSITE MONTPELLIER 2, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUEInventors: Yoann Guillemenet, Lionel Torres