Patents by Inventor Yoav Markus
Yoav Markus has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230393971Abstract: A system for distributed storage agents includes at least one memory and at least one compute node comprising at least one agent module. The at least one agent module is configured to cause at least a portion of data stored in the at least one memory to be pushed to a destination in accordance with an agent access plan.Type: ApplicationFiled: August 17, 2023Publication date: December 7, 2023Applicant: NeuroBlade Ltd.Inventors: Yoav MARKUS, Eliad HILLEL, Ilan MAYER-WOLF, Yaron KITTNER
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Publication number: 20230222123Abstract: Disclosed embodiments include an accelerated database management system including at least one processor including circuitry and a memory. The memory includes instructions that when executed by the circuitry cause the at least one processor to: receive an initial database query; generate a main query based on the initial database query; analyze the main query, and based on the analysis of the main query, generate at least a first sub-query and a second sub-query, wherein the second sub-query differs from the first sub-query; process the first sub-query along a first processing path to provide a first input to an execution module; process the second sub-query along a second processing path, different from the first processing path, to provide a second input to the execution module; and based on the first input and the second input received by the execution module, generate a main query result.Type: ApplicationFiled: March 15, 2023Publication date: July 13, 2023Applicant: NEUROBLADE LTD.Inventors: Opher REVIV, Eliad HILLEL, Yoav MARKUS
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Publication number: 20230222108Abstract: Disclosed embodiments include system including a hardware based, programmable data analytics processor configured to reside between a data storage unit and one or more hosts. The programmable data analytics processor includes a selector module configured to input a first set of data and, based on a selection indicator, output a first subset of the first set of data; a filter and project module configured to input a second set of data and, based on a function, output an updated second set of data; a join and group module configured to combine data from one or more third data sets into a combined data set; and a communications fabric configured to transfer data between any of the selector module, the filter and project module, and the join and group module.Type: ApplicationFiled: March 15, 2023Publication date: July 13, 2023Applicant: NEUROBLADE LTD.Inventors: Eliad HILLEL, Elad SITY, Gal DAYAN, Ilan MAYER-WOLF, Yoav MARKUS, Yaron KITTNER, Oded TRAININ, Gal HAI
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Publication number: 20230214389Abstract: A data pre-processing architecture may include an interface and a pruning logic configured to receive, via the interface, at least one filter value from a query processor; use the at least one filter value to scan rows or columns of a data table stored in a memory; generate a selection indicator identifying a set of rows or columns of the data table where the at least one filter value resides; and provide to the query processor a filtered output based on the selection indicator.Type: ApplicationFiled: March 15, 2023Publication date: July 6, 2023Applicant: NEUROBLADE LTD.Inventors: Oded TRAININ, Yoav MARKUS, Shai BETITO, Roman ZEYDE, Eliad HILLEL
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Patent number: 11500569Abstract: Systems, apparatus and methods for generation of XOR signature metadata and XOR signature management are presented. In one or more embodiments, a storage device controller includes a host interface, configured to receive one or more string lines (SLs) of data from a host, the one or more SLs to be programmed into a non-volatile memory (NVM), and processing circuitry. The processing circuitry is configured to, for each of the one or more SLs, generate signature metadata and provide the signature metadata in a header of the SL. The processing circuitry is still further configured to XOR two or more of the SLs with their respective signature metadata to generate a snapshot, and write the snapshot to the NVM.Type: GrantFiled: May 7, 2021Date of Patent: November 15, 2022Assignee: Western Digital Technologies, Inc.Inventors: Yoav Markus, Alexander Bazarsky, Alexander Kalmanovich
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Patent number: 11494125Abstract: A storage system and method for dual fast release and slow release responses are provided. In one embodiment, a storage system is provided comprising a volatile memory, a non-volatile memory, and a controller. The controller is configured to receive, from a host, a write command and data to be written in the non-volatile memory. The host comprises a command queue storing an identifier for the write command and a buffer storing a copy of the data. In response to storing the data in the volatile memory, the controller is configured to instruct the host to remove the identifier for the write command from the host's command queue. In response to successfully writing the data in the non-volatile memory, the controller is configured to instruct the host to remove the copy of the data from the host's buffer. Other embodiments are provided.Type: GrantFiled: February 19, 2021Date of Patent: November 8, 2022Assignee: Western Digital Technologies, Inc.Inventors: Yoav Markus, Nir Perry, Meytal Soffer, Alex Lemberg
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Patent number: 11449236Abstract: A memory controller that includes, in one implementation, a memory interface and a controller circuit. The memory interface is configured to interface with a non-volatile memory. The controller circuit is configured to receive a skewed codeword read from the non-volatile memory. The controller circuit is also configured to scan the skewed codeword by inserting or removing a quantity of bits at different locations in the skewed codeword and determining resulting syndrome weights of the skewed codeword. The controller circuit is further configured to determine an adjusted codeword by inserting or removing the quantity of bits at one of the different locations in the skewed codeword which results in a smallest syndrome weight. The controller circuit is also configured to decode the adjusted codeword.Type: GrantFiled: May 1, 2020Date of Patent: September 20, 2022Assignee: Western Digital Technologies, Inc.Inventors: David Avraham, Omer Fainzilber, Mark Shlick, Yoav Markus
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Publication number: 20220197557Abstract: A storage system and method for dual fast release and slow release responses are provided. In one embodiment, a storage system is provided comprising a volatile memory, a non-volatile memory, and a controller. The controller is configured to receive, from a host, a write command and data to be written in the non-volatile memory. The host comprises a command queue storing an identifier for the write command and a buffer storing a copy of the data. In response to storing the data in the volatile memory, the controller is configured to instruct the host to remove the identifier for the write command from the host's command queue. In response to successfully writing the data in the non-volatile memory, the controller is configured to instruct the host to remove the copy of the data from the host's buffer. Other embodiments are provided.Type: ApplicationFiled: February 19, 2021Publication date: June 23, 2022Applicant: Western Digital Technologies, Inc.Inventors: Yoav Markus, Nir Perry, Meytal Soffer, Alex Lemberg
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Publication number: 20210342095Abstract: A memory controller that includes, in one implementation, a memory interface and a controller circuit. The memory interface is configured to interface with a non-volatile memory. The controller circuit is configured to receive a skewed codeword read from the non-volatile memory. The controller circuit is also configured to scan the skewed codeword by inserting or removing a quantity of bits at different locations in the skewed codeword and determining resulting syndrome weights of the skewed codeword. The controller circuit is further configured to determine an adjusted codeword by inserting or removing the quantity of bits at one of the different locations in the skewed codeword which results in a smallest syndrome weight. The controller circuit is also configured to decode the adjusted codeword.Type: ApplicationFiled: May 1, 2020Publication date: November 4, 2021Inventors: David Avraham, Omer Fainzilber, Mark Shlick, Yoav Markus
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Publication number: 20210278987Abstract: Systems, apparatus and methods for generation of XOR signature metadata and XOR signature management are presented. In one or more embodiments, a storage device controller includes a host interface, configured to receive one or more string lines (SLs) of data from a host, the one or more SLs to be programmed into a non-volatile memory (NVM), and processing circuitry. The processing circuitry is configured to, for each of the one or more SLs, generate signature metadata and provide the signature metadata in a header of the SL. The processing circuitry is still further configured to XOR two or more of the SLs with their respective signature metadata to generate a snapshot, and write the snapshot to the NVM.Type: ApplicationFiled: May 7, 2021Publication date: September 9, 2021Applicant: Western Digital Technologies, Inc.Inventors: Yoav MARKUS, Alexander BAZARSKY, Alexander KALMANOVICH
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Patent number: 11086852Abstract: Disclosed are systems and methods for providing an improved hardware-assisted multi-table database with reduced memory footprint. A method includes receiving a request to perform an operation on a selected logical table of a plurality of logical database tables. The method also includes accessing a data structure comprising a plurality of records each including: a logical table identifier corresponding to one of the plurality of logical database tables, wherein the logical table identifier is accessed from a register, and at least one sort key. The method also includes performing the operation using one or more sort criteria, wherein the one or more sort criteria are maintained for the selected logical table using the at least one sort key of the plurality of records corresponding to the selected logical table. The method also includes updating the data structure to reflect the performed operation.Type: GrantFiled: June 27, 2019Date of Patent: August 10, 2021Assignee: Western Digital Technologies, Inc.Inventors: David Brief, Yoav Markus, Yuval Grossman
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Patent number: 11029874Abstract: Systems, apparatus and methods for generation of XOR signature metadata and XOR signature management are presented. In one or more embodiments, a storage device controller includes a host interface, configured to receive one or more string lines (SLs) of data from a host, the one or more SLs to be programmed into a non-volatile memory (NVM), and processing circuitry. The processing circuitry is configured to, for each of the one or more SLs, generate signature metadata and provide the signature metadata in a header of the SL. The processing circuitry is still further configured to XOR two or more of the SLs with their respective signature metadata to generate a snapshot, and write the snapshot to the NVM.Type: GrantFiled: July 30, 2019Date of Patent: June 8, 2021Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Yoav Markus, Alexander Bazarsky, Alexander Kalmanovich
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Patent number: 11030007Abstract: An arrangement is illustrated wherein a flash controller with a multi-constraints dynamic resource manager module configured to control both software and hardware clients is provided. The arrangement also provides for memory and an interface for connecting the controller to a host.Type: GrantFiled: December 19, 2017Date of Patent: June 8, 2021Assignee: WESTERN DIGITAL TECHNOLOGIES, INCInventors: David Chaim Brief, Yoav Markus, Shemmer Choresh
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Patent number: 11003387Abstract: An arrangement for providing a combined data and control signal for a multi die flash, comprising, a memory arrangement, the memory arrangement comprising at least two dies, a controller configured to send and receive signals to the memory arrangement and a common line connected to the memory arrangement and the controller and configured to transmit the signals from the controller to the at least two dies, wherein the arrangement is configured to provide a combined data and combined control signals to the multi-die flash.Type: GrantFiled: August 2, 2018Date of Patent: May 11, 2021Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Yoav Markus, Alexander Bazarsky
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Patent number: 10990316Abstract: An illustrative embodiment disclosed herein is an apparatus including a processor having programmed instructions that write data having mixed deletion characteristics sequentially to a plurality of data entries of a first physical erase block (PEB) in intermediate storage. The data having the mixed deletion characteristics includes first data having a first deletion characteristic. The processor has programmed instructions that maintain metadata in a plurality of metadata entries in a log. The metadata corresponds to the data having the mixed deletion characteristics. The processor has programmed instructions that identify, using the log, the first data having the first deletion characteristic and evacuate the first data having the first deletion characteristic to a second PEB in main memory.Type: GrantFiled: June 28, 2019Date of Patent: April 27, 2021Assignee: Western Digital Technologies, Inc.Inventors: Mikhael Zaidman, Yonatan Halevi, Judah Gamliel Hahn, Arseniy Aharonov, Yoav Markus
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Publication number: 20210034272Abstract: Systems, apparatus and methods for generation of XOR signature metadata and XOR signature management are presented. In one or more embodiments, a storage device controller includes a host interface, configured to receive one or more string lines (SLs) of data from a host, the one or more SLs to be programmed into a non-volatile memory (NVM), and processing circuitry. The processing circuitry is configured to, for each of the one or more SLs, generate signature metadata and provide the signature metadata in a header of the SL. The processing circuitry is still further configured to XOR two or more of the SLs with their respective signature metadata to generate a snapshot, and write the snapshot to the NVM.Type: ApplicationFiled: July 30, 2019Publication date: February 4, 2021Inventors: Yoav MARKUS, Alexander BAZARSKY, Alexander KALMANOVICH
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Patent number: 10891078Abstract: A method of sending a command from a slave storage device to a master host includes receiving an initial command from the master host. A callback response containing a requested command triggered by the initial command is sent by the slave storage device. In one embodiment, the master host is a Universal Flash Storage (UFS) host and the slave storage device is a UFS storage device. In one embodiment, the initial command is a start stop unit (SSU) command with a power condition field of sleep or powerdown and the requested command is a read buffer command. In another embodiment, the initial command is a start stop unit (SSU) command with a power condition field of active and the requested command is a write buffer command.Type: GrantFiled: March 29, 2019Date of Patent: January 12, 2021Assignee: Western Digital Technologies, Inc.Inventors: David C. Brief, Rotem Sela, Yoav Markus
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Publication number: 20200409588Abstract: An illustrative embodiment disclosed herein is an apparatus including a processor having programmed instructions that write data having mixed deletion characteristics sequentially to a plurality of data entries of a first physical erase block (PEB) in intermediate storage. The data having the mixed deletion characteristics includes first data having a first deletion characteristic. The processor has programmed instructions that maintain metadata in a plurality of metadata entries in a log. The metadata corresponds to the data having the mixed deletion characteristics. The processor has programmed instructions that identify, using the log, the first data having the first deletion characteristic and evacuate the first data having the first deletion characteristic to a second PEB in main memory.Type: ApplicationFiled: June 28, 2019Publication date: December 31, 2020Applicant: Western Digital Technologies, Inc.Inventors: Mikhael Zaidman, Yonatan Halevi, Judah Gamliel Hahn, Arseniy Aharonov, Yoav Markus
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Patent number: 10635352Abstract: Aspects of the disclosure provide for distributed flash interface module (FIM) processing in a solid state drive (SSD). Methods and apparatus lock a queue and retrieve a command from the queue. The command indicates an operation to be executed in conjunction with one or more non-volatile (NVM) dies of the SSD. The methods and apparatus then lock a NVM interface corresponding to the one or more NVM dies, determine whether the operation is a transfer operation, and execute the operation using the locked NVM interface according to whether the operation is the transfer operation. When the operation is determined to be the transfer operation, the queue is unlocked to allow execution of a second operation from the queue by a second controller in parallel with the operation executed by the controller. Thereafter, the NVM interface is unlocked after execution of the operation is complete.Type: GrantFiled: May 10, 2018Date of Patent: April 28, 2020Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Amir Shaharabany, Yoav Markus, Opher Lieber
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Publication number: 20200104295Abstract: Disclosed are systems and methods for providing an improved hardware-assisted multi-table database with reduced memory footprint. A method includes receiving a request to perform an operation on a selected logical table of a plurality of logical database tables. The method also includes accessing a data structure comprising a plurality of records each including: a logical table identifier corresponding to one of the plurality of logical database tables, wherein the logical table identifier is accessed from a register, and at least one sort key. The method also includes performing the operation using one or more sort criteria, wherein the one or more sort criteria are maintained for the selected logical table using the at least one sort key of the plurality of records corresponding to the selected logical table. The method also includes updating the data structure to reflect the performed operation.Type: ApplicationFiled: June 27, 2019Publication date: April 2, 2020Inventors: David BRIEF, Yoav MARKUS, Yuval GROSSMAN