Patents by Inventor Yoel Feler
Yoel Feler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240110780Abstract: A mosaic overlay target may include two or more cell sets distributed across a sample, wherein each cell set includes one or more cells, where each cell set is oriented to have at least one of mirror symmetry with respect to a central axis of the mosaic overlay target or rotational symmetry with respect to a central point of the mosaic overlay target. The cell sets may be configured according to a metrology recipe such that images of the mosaic overlay target generated based on the metrology recipe include metrology data suitable for two or more overlay measurements. A particular one of the overlay measurements may be based on portions of the images associated with at least one of the cell sets. At least two of the two or more overlay measurements may be alternative measurements of a common property of the sample.Type: ApplicationFiled: April 5, 2023Publication date: April 4, 2024Inventor: Yoel Feler
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Publication number: 20240035812Abstract: A metrology target includes a first target structure set having one or more first target structures formed within at least one of a first working zone or a second working zone of a sample. The metrology target includes a second target structure set having one or more second target structures formed within at least one of the first working zone or the second working zone. The first working zone may include a center of symmetry that overlaps with a center of symmetry of the second working zone when an overlay error of one or more layers of the sample is not present. The metrology target may additionally include a third target structure set, a fourth target structure set, or a fifth target structure set.Type: ApplicationFiled: May 8, 2023Publication date: February 1, 2024Inventors: Yoel Feler, Mark Ghinovker
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Patent number: 11862522Abstract: Methods, metrology modules and target designs are provided, which improve the accuracy of metrology measurements. Methods provide flexible handling of multiple measurement recipes and setups and enable relating them to landscape features that indicate their relation to resonance regions and to flat regions. Clustering of recipes, self-consistency tests, common processing of aggregated measurements, noise reduction, cluster analysis, detailed analysis of the landscape and targets with skewed cells are employed separately or in combination to provide cumulative improvements of measurement accuracy.Type: GrantFiled: February 18, 2021Date of Patent: January 2, 2024Inventors: Barak Bringoltz, Evgeni Gurevich, Ido Adam, Yoel Feler, Dror Alumot, Yuval Lamhot, Noga Sella, Yaron De Leeuw, Tal Yaziv, Eltsafon Ashwal-Island, Lilach Saltoun, Tom Leviant
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Patent number: 11862524Abstract: The present disclosure provides a target and a method of performing overlay measurements on a target. The target includes an array of cells comprising a first cell, a second cell, a third cell, and a fourth cell. Each cell includes a periodic structure with a pitch. The periodic structure includes a first section and a second section, separated by a first gap. The target further includes an electron beam overlay target, such that electron beam overlay measurements, advanced imaging metrology, and/or scatterometry measurements can be performed on the target.Type: GrantFiled: September 28, 2021Date of Patent: January 2, 2024Inventors: Inna Steely-Tarshish, Stefan Eyring, Mark Ghinovker, Yoel Feler, Eitan Hajaj, Ulrich Pohlmann, Nadav Gutman, Chris Steely, Raviv Yohanan, Ira Naot
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Publication number: 20230324810Abstract: Electron beam overlay targets and method of performing overlay measurements on a target using a semiconductor metrology tool are provided. One target includes a plurality of electron beam overlay elements and a plurality of two-dimensional elements that provide at least one two-dimensional imaging. The plurality of two dimensional elements are an array of evenly-spaced polygonal gratings across at least three rows and at least three columns. Another target includes a plurality of electron beam overlay elements and a plurality of AIMid elements. Each of the electron beam overlay elements includes at least two gratings that are overlaid at a perpendicular orientation to each other. The plurality of AIMid elements includes at least two gratings that are overlaid at a perpendicular orientation to each other.Type: ApplicationFiled: June 1, 2023Publication date: October 12, 2023Inventors: Inna Steely-Tarshish, Stefan Eyring, Mark Ghinovker, Yoel Feler, Eitan Hajaj, Ulrich Pohlmann, Nadav Gutman, Chris Steely, Raviv Yohanan, Ira Naot
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Patent number: 11774863Abstract: A method for semiconductor metrology includes depositing a first film layer on a semiconductor substrate and a second film layer overlying the first film layer. The first and second film layers are patterned to define a plurality of overlay targets comprising first target features formed in the first film layer having respective first locations, which are spaced apart by first nominal distances, and second target features formed in the second film layer having respective second locations, which are spaced apart by second nominal distances, which are different from the first nominal distances. An image of the semiconductor substrate is processed to measure respective displacements between the first and second target locations in each of the overlay targets, and to estimate both an actual overlay error between the patterning of the first and second film layers and a measurement error of the imaging assembly.Type: GrantFiled: October 21, 2021Date of Patent: October 3, 2023Assignee: KLA CORPORATIONInventors: Mark Ghinovker, Yoel Feler
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Publication number: 20230281779Abstract: A method of semiconductor metrology includes patterning a film layer on a semiconductor substrate to define a first field on the semiconductor substrate with a first pattern comprising at least a first target feature within a first margin along a first edge of the first field and to define a second field, which abuts the first field, with a second pattern comprising at least a second target feature within a second margin along a second edge of the second field, such that the second edge of the second field adjoins the first edge of the first field. The first target feature in the first margin is adjacent to the second target feature in the second margin without overlapping the second target feature. An image is captured of at least the first and second target features and is processed to detect a misalignment between the first and second fields.Type: ApplicationFiled: March 3, 2022Publication date: September 7, 2023Inventors: Mark GHINOVKER, Yoel FELER
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Patent number: 11720031Abstract: Combined electron beam overlay and scatterometry overlay targets include first and second periodic structures with gratings. Gratings in the second periodic structure can be positioned under the gratings of the first periodic structure or can be positioned between the gratings of the first periodic structure. These overlay targets can be used in semiconductor manufacturing.Type: GrantFiled: September 28, 2021Date of Patent: August 8, 2023Assignee: KLA CorporationInventors: Inna Steely-Tarshish, Stefan Eyring, Mark Ghinovker, Yoel Feler, Eitan Hajaj, Ulrich Pohlmann, Nadav Gutman, Chris Steely, Raviv Yohanan, Ira Naot
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Patent number: 11686576Abstract: A metrology target includes a first target structure set having one or more first target structures formed within at least one of a first working zone or a second working zone of a sample. The metrology target includes a second target structure set having one or more second target structures formed within at least one of the first working zone or the second working zone. The first working zone may include a center of symmetry that overlaps with a center of symmetry of the second working zone when an overlay error of one or more layers of the sample is not present. The metrology target may additionally include a third target structure set, a fourth target structure set, or a fifth target structure set.Type: GrantFiled: November 16, 2020Date of Patent: June 27, 2023Assignee: KLA CorporationInventors: Yoel Feler, Mark Ghinovker
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Publication number: 20230129618Abstract: A method for semiconductor metrology includes depositing a first film layer on a semiconductor substrate and a second film layer overlying the first film layer. The first and second film layers are patterned to define a plurality of overlay targets comprising first target features formed in the first film layer having respective first locations, which are spaced apart by first nominal distances, and second target features formed in the second film layer having respective second locations, which are spaced apart by second nominal distances, which are different from the first nominal distances. An image of the semiconductor substrate is processed to measure respective displacements between the first and second target locations in each of the overlay targets, and to estimate both an actual overlay error between the patterning of the first and second film layers and a measurement error of the imaging assembly.Type: ApplicationFiled: October 21, 2021Publication date: April 27, 2023Inventors: Mark Ghinovker, Yoel Feler
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Publication number: 20230099105Abstract: Metrology methods and targets are provided for reducing or eliminating a difference between a device pattern position and a target pattern position while maintaining target printability, process compatibility and optical contrast—in both imaging and scatterometry metrology. Pattern placement discrepancies may be reduced by using sub-resolved assist features in the mask design which have a same periodicity (fine pitch) as the periodic structure and/or by calibrating the measurement results using PPE (pattern placement error) correction factors derived by applying learning procedures to specific calibration terms, in measurements and/or simulations. Metrology targets are disclosed with multiple periodic structures at the same layer (in addition to regular target structures), e.g., in one or two layers, which are used to calibrate and remove PPE, especially when related to asymmetric effects such as scanner aberrations, off-axis illumination and other error sources.Type: ApplicationFiled: December 6, 2022Publication date: March 30, 2023Inventors: Yoel Feler, Vladimir Levinski, Roel Gronheid, Sharon Aharon, Evgeni Gurevich, Anna Golotsvan, Mark Ghinovker
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Patent number: 11614692Abstract: A grating for use in metrology including a periodic structure including a plurality of units having a pitch P, at least one unit of the plurality of units including at least a first periodic sub-structure having a first sub-pitch P1 smaller than the pitch P, and at least a second periodic sub-structure arranged along-side and separated from the first periodic sub-structure within the at least one unit and having a second sub-pitch P2 smaller than the pitch P and different from the first sub-pitch P1, P1 and P2 being selected to yield at least one Moir pitch Pm=P1·P2/(P2?P1), the pitch P being an integer multiple of the first sub-pitch P and of the second sub-pitch P2.Type: GrantFiled: March 20, 2020Date of Patent: March 28, 2023Assignee: KLA CorporationInventors: Vladimir Levinski, Yoel Feler
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Patent number: 11604149Abstract: A metrology system configured to measure overlay errors on a sample is disclosed. The metrology system measures overlay error on the sample in a first direction and/or a second direction simultaneously or sequentially. The metrology system comprises an illumination sub-system configured to illuminate a hatched overlay target on the sample with one or more illumination lobes. The metrology system further comprises an objective lens and a detector at an image plane configured to image the hatched overlay target. A controller is configured to direct illumination source to generate the illumination lobes, receive images of the hatched overlay target, and calculate the overlay errors between a first layer of the sample and a second layer of the sample.Type: GrantFiled: January 6, 2021Date of Patent: March 14, 2023Assignee: KLA CorporationInventor: Yoel Feler
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Publication number: 20230068016Abstract: A system and method for generating an angular calibration factor (ACF) for a metrology tool useful in a fabrication process, the method including providing the metrology tool, the metrology tool including a stage and a housing, measuring a rotational orientation of the stage relative to the housing and generating the ACF for the stage based at least partially on the rotational orientation.Type: ApplicationFiled: August 26, 2021Publication date: March 2, 2023Inventors: Alexander Novikov, Amnon Manassen, Ido Dolev, Yuri Paskover, Nir Ben David, Yoel Feler, Yoram Uziel
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Publication number: 20220413394Abstract: Combined electron beam overlay and scatterometry overlay targets include first and second periodic structures with gratings. Gratings in the second periodic structure can be positioned under the gratings of the first periodic structure or can be positioned between the gratings of the first periodic structure. These overlay targets can be used in semiconductor manufacturing.Type: ApplicationFiled: September 28, 2021Publication date: December 29, 2022Inventors: Inna Steely-Tarshish, Stefan Eyring, Mark Ghinovker, Yoel Feler, Eitan Hajaj, Ulrich Pohlmann, Nadav Gutman, Chris Steely, Raviv Yohanan, Ira Naot
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Publication number: 20220415725Abstract: The present disclosure provides a target and a method of performing overlay measurements on a target. The target includes an array of cells comprising a first cell, a second cell, a third cell, and a fourth cell. Each cell includes a periodic structure with a pitch. The periodic structure includes a first section and a second section, separated by a first gap. The target further includes an electron beam overlay target, such that electron beam overlay measurements, advanced imaging metrology, and/or scatterometry measurements can be performed on the target.Type: ApplicationFiled: September 28, 2021Publication date: December 29, 2022Inventors: Inna Steely-Tarshish, Stefan Eyring, Mark Ghinovker, Yoel Feler, Eitan Hajaj, Ulrich Pohlmann, Nadav Gutman, Chris Steely, Raviv Yohanan, Ira Naot
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Publication number: 20220413395Abstract: Electron beam overlay targets and method of performing overlay measurements on a target using a semiconductor metrology tool are provided. One target includes a plurality of electron beam overlay elements and a plurality of two-dimensional elements that provide at least one two-dimensional imaging. The plurality of two dimensional elements are an array of evenly-spaced polygonal gratings across at least three rows and at least three columns. Another target includes a plurality of electron beam overlay elements and a plurality of AIMid elements. Each of the electron beam overlay elements includes at least two gratings that are overlaid at a perpendicular orientation to each other. The plurality of AIMid elements includes at least two gratings that are overlaid at a perpendicular orientation to each other.Type: ApplicationFiled: September 28, 2021Publication date: December 29, 2022Inventors: Inna Steely-Tarshish, Stefan Eyring, Mark Ghinovker, Yoel Feler, Eitan Hajaj, Ulrich Pohlmann, Nadav Gutman, Chris Steely, Raviv Yohanan, Ira Naot
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Patent number: 11537043Abstract: Metrology methods and targets are provided for reducing or eliminating a difference between a device pattern position and a target pattern position while maintaining target printability, process compatibility and optical contrast—in both imaging and scatterometry metrology. Pattern placement discrepancies may be reduced by using sub-resolved assist features in the mask design which have a same periodicity (fine pitch) as the periodic structure and/or by calibrating the measurement results using PPE (pattern placement error) correction factors derived by applying learning procedures to specific calibration terms, in measurements and/or simulations. Metrology targets are disclosed with multiple periodic structures at the same layer (in addition to regular target structures), e.g., in one or two layers, which are used to calibrate and remove PPE, especially when related to asymmetric effects such as scanner aberrations, off-axis illumination and other error sources.Type: GrantFiled: January 28, 2021Date of Patent: December 27, 2022Assignee: KLA-TENCOR CORPORATIONInventors: Yoel Feler, Vladimir Levinski, Roel Gronheid, Sharon Aharon, Evgeni Gurevich, Anna Golotsvan, Mark Ghinovker
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Publication number: 20220357674Abstract: An overlay metrology system may include an overlay metrology tool suitable for measurement of an overlay target on a sample, the overlay target including one or more grating structures with patterned features distributed along one or more measurement directions. The overlay metrology tool may include an objective lens and an illumination pathway to illuminate the overlay target with two or more oblique illumination lobes distributed among one or more illumination distributions such that, for each of the measurement directions, diffraction orders of the one or more illumination distributions by the overlay target that are collected by the objective lens exclusively include a 0-order diffraction lobe and a single first-order diffraction lobe from at least one of the two or more illumination lobes. The overlay metrology tool may further include at least one detector to image the sample and a controller to generate overlay measurements based on the images.Type: ApplicationFiled: March 1, 2022Publication date: November 10, 2022Inventors: Andrew V. Hill, Yoel Feler, Amnon Manassen, Mark Ghinovker, Yonatan Vaknin
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Publication number: 20220199437Abstract: A method for measurement of misregistration in the manufacture of semiconductor device wafers, the method including measuring misregistration between layers of a semiconductor device wafer at a first instance and providing a first misregistration indication, measuring misregistration between layers of a semiconductor device wafer at a second instance and providing a second misregistration indication, providing a misregistration measurement difference output in response to a difference between the first misregistration indication and the second misregistration indication, providing a baseline difference output and ameliorating the difference between the misregistration measurement difference output and the baseline difference output.Type: ApplicationFiled: March 7, 2022Publication date: June 23, 2022Inventors: Roie Volkovich, Renan Milo, Liran Yerushalmi, Moran Zaberchik, Yoel Feler, David Izraeli