Patents by Inventor Yogendra Singh Sikarwar

Yogendra Singh Sikarwar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11971775
    Abstract: Various processes for efficiently and effectively determining or predicting whether data stored in a non-volatile storage device is unreadable and/or unrecoverable during a read-retry process. To make the determination, different dynamic read threshold (DRT) entries of a dynamic read threshold (DRT) table are applied, in parallel, across different planes of the non-volatile storage device to determine whether the data is unreadable and/or unrecoverable.
    Type: Grant
    Filed: September 16, 2022
    Date of Patent: April 30, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Yogendra Singh Sikarwar, Prateek Kumar TR
  • Publication number: 20240095115
    Abstract: Various processes for efficiently and effectively determining or predicting whether data stored in a non-volatile storage device is unreadable and/or unrecoverable during a read-retry process. To make the determination, different dynamic read threshold (DRT) entries of a dynamic read threshold (DRT) table are applied, in parallel, across different planes of the non-volatile storage device to determine whether the data is unreadable and/or unrecoverable.
    Type: Application
    Filed: September 16, 2022
    Publication date: March 21, 2024
    Inventors: Yogendra Singh Sikarwar, Prateek Kumar TR
  • Patent number: 11442666
    Abstract: A storage system has a memory with primary and secondary blocks. Data is stored redundantly in the primary and secondary memory blocks but in a different programming order. For example, data is programmed in the first memory block starting at a first wordline and ending at a last wordline, while data is programmed in the second memory block starting at the last wordline and ending at the first wordline.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: September 13, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Yogendra Singh Sikarwar, Ankit Naghate, Milind Giradkar, Rakshit Tikoo
  • Publication number: 20220155999
    Abstract: A storage system has a memory with primary and secondary blocks. Data is stored redundantly in the primary and secondary memory blocks but in a different programming order. For example, data is programmed in the first memory block starting at a first wordline and ending at a last wordline, while data is programmed in the second memory block starting at the last wordline and ending at the first wordline.
    Type: Application
    Filed: February 23, 2021
    Publication date: May 19, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventors: Yogendra Singh Sikarwar, Ankit Naghate, Milind Giradkar, Rakshit Tikoo
  • Patent number: 11231883
    Abstract: A memory device includes logic to detect the last page written in multi-plane non-volatile memory. The device includes a memory array, and a storage controller. The memory array includes multiple planes and multiple word lines operable on the memory array. The storage controller is configured to divide the word lines into contiguous sub-ranges and assign a subset of the word lines to boundaries of the sub-ranges. Each word line of the subset of word lines is assigned to a page in a different one of the memory planes. The controller operates the subset of word lines to sense a page programmed or erased state from each of the memory planes in parallel.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: January 25, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ankit Vijay Naghate, Rakshit Tikoo, Yogendra Singh Sikarwar, Ashish Singla, Arun Thandapani, Lee M Gavens
  • Publication number: 20220004336
    Abstract: A memory device includes logic to detect the last page written in multi-plane non-volatile memory. The device includes a memory array, and a storage controller. The memory array includes multiple planes and multiple word lines operable on the memory array. The storage controller is configured to divide the word lines into contiguous sub-ranges and assign a subset of the word lines to boundaries of the sub-ranges. Each word line of the subset of word lines is assigned to a page in a different one of the memory planes. The controller operates the subset of word lines to sense a page programmed or erased state from each of the memory planes in parallel.
    Type: Application
    Filed: July 2, 2020
    Publication date: January 6, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventors: Ankit Vijay Naghate, Rakshit Tikoo, Yogendra Singh Sikarwar, Ashish Singla, Arun Thandapani, Lee M. Gavens
  • Patent number: 11036407
    Abstract: A storage system and method for smart folding are provided. In one example, the storage system has a memory with a plurality of single level cell (SLC) blocks and a multi-level cell (MLC) block. The MLC block has a plurality of pages, each with a different sense time. The storage system tracks a read count of each of the plurality of SLC blocks and determines how to fold the plurality of SLC blocks into the plurality of pages based on the read count of each of the plurality of SLC blocks and the sense time of each of the plurality of pages. In this way, SLC blocks with higher read counts can be folded into pages that have faster sense times.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: June 15, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Rakshit Tikoo, Ankit Naghate, Yogendra Singh Sikarwar, Arun Thandapani