Patents by Inventor Yogesh Bansal
Yogesh Bansal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11977638Abstract: Disclosed are techniques for performing a low-impact firmware update to a first microcontroller. In an aspect, a security entity communicatively coupled to the first microcontroller receives an update to firmware of the first microcontroller, authenticates the update to the firmware of the first microcontroller to prevent a security-related rollback, offloads system management tasks and interrupt handling from the first microcontroller to at least a second microcontroller communicatively coupled to the first microcontroller, coordinates installation of the update to the firmware of the first microcontroller without taking processing cycles from host software, and restores, to the first microcontroller, system management states occurring after the system management tasks and interrupt handling are offloaded from the first microcontroller.Type: GrantFiled: June 29, 2022Date of Patent: May 7, 2024Assignee: Ampere Computing LLCInventors: Sachhidh Kannan, Shivnandan Kaushik, Harb Abdulhamid, Yogesh Bansal, Vanshidhar Konda
-
Patent number: 11966750Abstract: Disclosed are techniques for management of multiple processor cores in a multi-core system-on-chip (SoC). In an implementation, the SoC may configure each processor core in a first subset of processor cores as a management controller for performing system management functions for processor cores not in the first subset, the first subset comprising at least one processor core from the plurality of processor cores. System management functions are handled by the processor cores in the first subset, while operating system functions are handled by the processor cores not in the first subset. In an implementation, the number of processor cores to be included in the first subset (which may be zero if it is desired that the SoC may operate in legacy mode), may be controlled at boot time according to a boot setting.Type: GrantFiled: June 29, 2022Date of Patent: April 23, 2024Assignee: Ampere Computing LLCInventors: Shivnandan Kaushik, Harb Abdulhamid, Vanshidhar Konda, Yogesh Bansal, Sachhidh Kannan, Sebastien Hily
-
Patent number: 11962621Abstract: A method includes receiving, by a computer system, information related to device health of an electronic device, determining, by the computer system, a health status of the electronic device based at least in part on the received information related to the device health of the electronic device, requesting, by a switch having a port connected to the electronic device, the health status of the electronic device from the computer system, receiving, by the computer system, the request for the health status of the electronic device from the switch, transmitting, by the computer system, the health status of the electronic device to the switch, evaluating, by the switch, the transmitted health status of the electronic device using network access rules associated corresponding to health statuses, and applying, by the switch, a network access control configuration to the port of the switch based on the evaluating the transmitted health status.Type: GrantFiled: May 20, 2022Date of Patent: April 16, 2024Assignee: Sophos LimitedInventors: Biju Ramachandra Kaimal, Andrew J. Thomas, Kerav Vaidya, Yogesh Bansal, Robert Paul Andrews
-
Publication number: 20240005003Abstract: Disclosed are techniques for performing a low-impact firmware update to a first microcontroller. In an aspect, a security entity communicatively coupled to the first microcontroller receives an update to firmware of the first microcontroller, authenticates the update to the firmware of the first microcontroller to prevent a security-related rollback, offloads system management tasks and interrupt handling from the first microcontroller to at least a second microcontroller communicatively coupled to the first microcontroller, coordinates installation of the update to the firmware of the first microcontroller without taking processing cycles from host software, and restores, to the first microcontroller, system management states occurring after the system management tasks and interrupt handling are offloaded from the first microcontroller.Type: ApplicationFiled: June 29, 2022Publication date: January 4, 2024Inventors: Sachhidh KANNAN, Shivnandan KAUSHIK, Harb ABDULHAMID, Yogesh BANSAL, Vanshidhar KONDA
-
Publication number: 20240004668Abstract: Disclosed are techniques for management of multiple processor cores in a multi-core system-on-chip (SoC). In an implementation, the SoC may configure each processor core in a first subset of processor cores as a management controller for performing system management functions for processor cores not in the first subset, the first subset comprising at least one processor core from the plurality of processor cores. System management functions are handled by the processor cores in the first subset, while operating system functions are handled by the processor cores not in the first subset. In an implementation, the number of processor cores to be included in the first subset (which may be zero if it is desired that the SoC may operate in legacy mode), may be controlled at boot time according to a boot setting.Type: ApplicationFiled: June 29, 2022Publication date: January 4, 2024Inventors: Shivnandan KAUSHIK, Harb ABDULHAMID, Vanshidhar KONDA, Yogesh BANSAL, Sachhidh KANNAN, Sebastien HILY
-
Publication number: 20230319113Abstract: A method includes receiving, by a computer system, information related to device health of an electronic device, determining, by the computer system, a health status of the electronic device based at least in part on the received information related to the device health of the electronic device, requesting, by a switch having a port connected to the electronic device, the health status of the electronic device from the computer system, receiving, by the computer system, the request for the health status of the electronic device from the switch, transmitting, by the computer system, the health status of the electronic device to the switch, evaluating, by the switch, the transmitted health status of the electronic device using network access rules associated corresponding to health statuses, and applying, by the switch, a network access control configuration to the port of the switch based on the evaluating the transmitted health status.Type: ApplicationFiled: May 20, 2022Publication date: October 5, 2023Inventors: Biju Ramachandra Kaimal, Andrew J. Thomas, Kerav Vaidya, Yogesh Bansal
-
Publication number: 20230261935Abstract: The techniques disclosed herein provision inter-DC WAN capacity based on network failure statistics and bandwidth demands of a cloud-hosted application. Network capacity is provisioned based on an assumption of runtime cooperation between the application and the network. For example, if the network detects that a link has failed, the application may cooperate with the network to pause a deferrable transfer, reserving bandwidth for non-deferrable transfers. With knowledge that deferrable transfers will be dynamically paused when a primary link fails, backup links may be provisioned with less capacity than the primary link. The ability to dynamically defer transfers also enables a greater degree of bandwidth smoothing, e.g. reducing peak demand by scheduling deferrable transfers for off-peak hours. This allows network links to be provisioned with less capacity than if all transfers were performed immediately.Type: ApplicationFiled: February 17, 2022Publication date: August 17, 2023Inventors: Ranjita BHAGWAN, Harsha SHARMA, Parth Dhaval THAKKAR, Sagar Bharadwaj KALASIBAIL SEETHARAM, Venkata N. PADMANABHAN, Kathleen VOELBEL, Vijay RAJESHKUMAR, Yogesh BANSAL
-
Publication number: 20230236651Abstract: A single communication fabric for a data processing apparatus is provided. The fabric has an interconnection network to provide a topology of data communication channels between a plurality of data-handling functional units. The interconnection network has a first interconnection domain to provide data communication between a first subset of the data-handling functional units and a second interconnection domain to provide data communication between a second subset of the data-handling functional units. The power management circuitry is arranged to control a first performance level for the first interconnection domain independently from control of a second performance level for the second interconnection domain. Machine readable instructions and a method are provided to concurrently set performance levels of two different fabric domains to respective different operating frequencies.Type: ApplicationFiled: June 26, 2020Publication date: July 27, 2023Inventors: UJJWAL GUPTA, ANKUSH VARMA, LAKSHMIPRIYA SESHAN, NIKETHAN SHIVANAND BALIGAR, NIKHIL GUPTA, SWADESH CHOUDHARY, YOGESH BANSAL
-
Publication number: 20230205948Abstract: Systems and methods for completion design are disclosed. Wellsite data is acquired for one or more existing production wells. The wellsite data is transformed into model data sets for training a first machine learning (ML) model to predict well logs. A first well model uses the well logs to estimate production of the existing well(s). Parameters of the first well model are tuned based on a comparison between the estimated and actual production of the existing well(s). A second ML model is trained to predict parameters of a second well model for a new well, based on the tuned parameters of the first well model. The new well's production is forecasted using the second ML model. Completion costs for the new well are estimated based on the well's completion design parameters and the forecasted production. Completion design parameters are adjusted, based on the estimated completion costs and the forecasted production.Type: ApplicationFiled: December 23, 2021Publication date: June 29, 2023Inventors: Yogesh Bansal, Gerardo Mijares
-
Publication number: 20230193754Abstract: Systems and methods for machine learning (ML) assisted parameter matching are disclosed. Wellsite data is acquired for one or more existing production wells in a hydrocarbon producing field. The wellsite data is transformed into one or more model data sets for predictive modeling. A first ML model is trained to predict well logs for the existing production well(s), based on the model data set(s). A first well model is generated to estimate production of the existing production well(s) based on the predicted well logs. Parameters of the first well model are tuned based on a comparison between the estimated and an actual production of the existing production well(s). A second ML model is trained to predict parameters of a second well model for a new production well, based on the tuned parameters of the first well model. The new well’s production is forecasted using the second ML model.Type: ApplicationFiled: December 20, 2021Publication date: June 22, 2023Inventors: Yogesh Bansal, Gerardo Mijares
-
Patent number: 11567555Abstract: Embodiments include an apparatus comprising an execution unit coupled to a memory, a microcode controller, and a hardware controller. The microcode controller is to identify a global power and performance hint in an instruction stream that includes first and second instruction phases to be executed in parallel, identify a local hint based on synchronization dependence in the first instruction phase, and use the first local hint to balance power consumption between the execution unit and the memory during parallel executions of the first and second instruction phases. The hardware controller is to use the global hint to determine an appropriate voltage level of a compute voltage and a frequency of a compute clock signal for the execution unit during the parallel executions of the first and second instruction phases. The first local hint includes a processing rate for the first instruction phase or an indication of the processing rate.Type: GrantFiled: August 30, 2019Date of Patent: January 31, 2023Assignee: Intel CorporationInventors: Jason Seung-Min Kim, Sundar Ramani, Yogesh Bansal, Nitin N. Garegrat, Olivia K. Wu, Mayank Kaushik, Mrinal Iyer, Tom Schebye, Andrew Yang
-
Patent number: 11379431Abstract: A system for write optimization in transactional data management systems is described. The system stores a tree data structure that comprises a root, a plurality of internal nodes, and a plurality of leaf nodes. Each internal node comprises a pivot key and a child pointer. Each leaf node stores key-value pairs sorted by a corresponding key. The system forms a plurality of hybrid nodes. The hybrid nodes comprise a layer of internal nodes that are immediate parents of the plurality of leaf nodes. A buffer is formed only for each internal node of the plurality of hybrid nodes. The buffer is used to store a message that encodes an operation. The message is to be applied to the corresponding leaf nodes of the plurality of hybrid nodes.Type: GrantFiled: December 9, 2019Date of Patent: July 5, 2022Assignee: Microsoft Technology Licensing, LLCInventors: Yogesh Bansal, Anil Ruia, Alexandre Costa, Tobias Klima, Brett Shirley, Ian Jose, Andrew Goodsell, Serguei Martchenko, Umair Ahmad
-
Publication number: 20220100247Abstract: Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.Type: ApplicationFiled: September 26, 2020Publication date: March 31, 2022Applicant: Intel CorporationInventors: Vivek Garg, Ankush Varma, Krishnakanth Sistla, Nikhil Gupta, Nikethan Shivanand Baligar, Stephen Wang, Nilanjan Palit, Timothy Kam, Adwait Purandare, Ujjwal Gupta, Stanley Chen, Dorit Shapira, Shruthi Venugopal, Suresh Chemudupati, Rupal Parikh, Eric Dehaemer, Pavithra Sampath, Phani Kumar Kandula, Yogesh Bansal, Dean Mulla, Michael Tulanowski, Stephen Haake, Andrew Herdrich, Ripan Das
-
Publication number: 20220027493Abstract: A server kernel processing system receives an input/output (I/O) request from a user mode computing environment. The I/O request is analyzed to determine whether it is a modification request to modify data in a target volume. If so, target analysis logic determines whether the request is for a target volume that is within a first or second protected volume. If the request is to modify data stored in the first protected volume, the request is blocked. If the request is to modify data in a second protected volume, then a whitelist is examined to determine whether the requesting process and user are on the whitelist. If not, the request is also blocked.Type: ApplicationFiled: June 29, 2021Publication date: January 27, 2022Inventors: Dhananjay Ramakrishnappa, Gregory Irving Thiel, Manoharan Kuppusamy, Yogesh Bansal
-
Patent number: 11080416Abstract: A server kernel processing system receives an input/output (I/O) request from a user mode computing environment. The I/O request is analyzed to determine whether it is a modification request to modify data in a target volume. If so, target analysis logic determines whether the request is for a target volume that is within a first or second protected volume. If the request is to modify data stored in the first protected volume, the request is blocked. If the request is to modify data in a second protected volume, then a whitelist is examined to determine whether the requesting process and user are on the whitelist. If not, the request is also blocked.Type: GrantFiled: October 8, 2018Date of Patent: August 3, 2021Assignee: Microsoft technology Licensing, LLCInventors: Dhananjay Ramakrishnappa, Gregory Irving Thiel, Manoharan Kuppusamy, Yogesh Bansal
-
Publication number: 20210173819Abstract: A system for write optimization in transactional data management systems is described. The system stores a tree data structure that comprises a root, a plurality of internal nodes, and a plurality of leaf nodes. Each internal node comprises a pivot key and a child pointer. Each leaf node stores key-value pairs sorted by a corresponding key. The system forms a plurality of hybrid nodes. The hybrid nodes comprise a layer of internal nodes that are immediate parents of the plurality of leaf nodes. A buffer is formed only for each internal node of the plurality of hybrid nodes. The buffer is used to store a message that encodes an operation. The message is to be applied to the corresponding leaf nodes of the plurality of hybrid nodes.Type: ApplicationFiled: December 9, 2019Publication date: June 10, 2021Inventors: Yogesh Bansal, Anil Ruia, Alexandre Costa, Tobias Klima, Brett Shirley, Ian Jose, Andrew Goodsell, Serguei Martchenko, Umair Ahmad
-
Patent number: 10713279Abstract: Systems, methods, and software are disclosed that provide enhanced replication for message services. In one implementation, updates to a replication source are replicated to replication targets. The replication is monitored to identify an individual health of the replication for each of the replication targets. A composite health of the replication is determined based on the individual health of the replication for each of the replication targets. The updates to the replication source are then controlled based on the composite health of the replication.Type: GrantFiled: July 19, 2018Date of Patent: July 14, 2020Assignee: Microsoft Technology Licensing, LLCInventors: Gregory I. Thiel, David Sterling, Sabitha Abraham, Yogesh Bansal, Nikita Kozhekin
-
Publication number: 20200110892Abstract: A server kernel processing system receives an input/output (I/O) request from a user mode computing environment. The I/O request is analyzed to determine whether it is a modification request to modify data in a target volume. If so, target analysis logic determines whether the request is for a target volume that is within a first or second protected volume. If the request is to modify data stored in the first protected volume, the request is blocked. If the request is to modify data in a second protected volume, then a whitelist is examined to determine whether the requesting process and user are on the whitelist. If not, the request is also blocked.Type: ApplicationFiled: October 8, 2018Publication date: April 9, 2020Inventors: Dhananjay Ramakrishnappa, Gregory Irving Thiel, Manoharan Kuppusamy, Yogesh Bansal
-
Publication number: 20190384370Abstract: Embodiments include an apparatus comprising an execution unit coupled to a memory, a microcode controller, and a hardware controller. The microcode controller is to identify a global power and performance hint in an instruction stream that includes first and second instruction phases to be executed in parallel, identify a local hint based on synchronization dependence in the first instruction phase, and use the first local hint to balance power consumption between the execution unit and the memory during parallel executions of the first and second instruction phases. The hardware controller is to use the global hint to determine an appropriate voltage level of a compute voltage and a frequency of a compute clock signal for the execution unit during the parallel executions of the first and second instruction phases. The first local hint includes a processing rate for the first instruction phase or an indication of the processing rate.Type: ApplicationFiled: August 30, 2019Publication date: December 19, 2019Inventors: Jason Seung-Min Kim, Sundar Ramani, Yogesh Bansal, Nitin N. Garegrat, Olivia K. Wu, Mayank Kaushik, Mrinal Iyer, Tom Schebye, Andrew Yang
-
Publication number: 20180322182Abstract: Systems, methods, and software are disclosed that provide enhanced replication for message services. In one implementation, updates to a replication source are replicated to replication targets. The replication is monitored to identify an individual health of the replication for each of the replication targets. A composite health of the replication is determined based on the individual health of the replication for each of the replication targets. The updates to the replication source are then controlled based on the composite health of the replication.Type: ApplicationFiled: July 19, 2018Publication date: November 8, 2018Inventors: Gregory I. Thiel, David Sterling, Sabitha Abraham, Yogesh Bansal, Nikita Kozhekin