Patents by Inventor Yogesh Dilip SAVE

Yogesh Dilip SAVE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory efficient scalable distributed static timing analysis using structure based self-aligned parallel partitioning
    Patent number: 11922106
    Abstract: A method includes extracting information associated with constraints and clock information from a file of a circuit design; determining a topological cone based on the extracted information for a partition of two or more partitions of the circuit design, and performing timing analysis on the partition of the two or more partitions based on the topological cone. The topological cone includes objects associated with the partition of the two or more partitions of the circuit design.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: March 5, 2024
    Assignee: SYNOPSYS, INC.
    Inventors: Abhishek Nandi, Qiuyang Wu, Yogesh Dilip Save
  • RUNTIME AND MEMORY EFFICIENT ATTRIBUTE QUERY HANDLING FOR DISTRIBUTED ENGINE
    Publication number: 20220318481
    Abstract: A method, a system, and a non-transitory computer readable medium are provided. The method includes performing, by one or more computing devices, a lookahead scan of a file of a circuit design to extract information associated with a query in an iterative loop, performing an action to retrieve attribute information from one or more partitions of the circuit design before executing the iterative loop, and querying the iterative loop using the stored attribute information. The action stores the attribute information based on the extracted information.
    Type: Application
    Filed: April 1, 2022
    Publication date: October 6, 2022
    Applicant: Synopsys, Inc.
    Inventors: Yogesh Dilip SAVE, Kirti Kedia, Ajit Sequeira, Abhishek Nandi
  • MEMORY EFFICIENT SCALABLE DISTRIBUTED STATIC TIMING ANALYSIS USING STRUCTURE BASED SELF-ALIGNED PARALLEL PARTITIONING
    Publication number: 20220027542
    Abstract: A method includes extracting information associated with constraints and clock information from a file of a circuit design; determining a topological cone based on the extracted information for a partition of two or more partitions of the circuit design, and performing timing analysis on the partition of the two or more partitions based on the topological cone. The topological cone includes objects associated with the partition of the two or more partitions of the circuit design.
    Type: Application
    Filed: July 23, 2021
    Publication date: January 27, 2022
    Inventors: Abhishek NANDI, Qiuyang WU, Yogesh Dilip SAVE