Abstract: An electronic device includes a doped semiconductor substrate of a first conductivity type. First and second doped wells are provided, separated from each other by trench isolation, within the doped semiconductor substrate. At least one first region and at least one second region are respectively located in the first and second doped wells, with each first and second region having a doping level higher than a doping level of the first and second doped wells. The trench isolation penetrates into the first and second doped wells and extends laterally between the first region and second region. A third region laterally extends between the first and second doped wells at a location under the insulating trench. The third region has a doping level lower than the doping level of the first and second doped wells.

Abstract: An electronic device includes a doped semiconductor substrate of a first conductivity type. A first doped well of a second conductivity type opposite to the first conductivity type extends into the doped semiconductor substrate from a surface thereof. A second doped well of the first conductivity type is located in the first well. A third electrically-insulating well is located in the second well. A fourth doped well of the first conductivity type is located in the third well. First, second, and third doped regions of the first conductivity type are respectively located in the doped semiconductor substrate, the second doped well and the fourth doped well. The first, second, and third doped regions have doping levels greater than a doping level of the doped semiconductor substrate. A fourth doped region the second conductivity type is located in the fourth doped well adjacent the second doped region.

Abstract: A microelectronic component is capable of being used as a memory cell. The component includes a semiconductor layer resting on an insulating layer and including a doped source region of a first conductivity type, a doped drain region of a second conductivity type, and an intermediate region, non-doped or more lightly doped, with the second conductivity type, than the drain region, the intermediate region including first and second portions respectively extending from the drain region and from the source region. An insulated front gate electrode rests on the first portion. A first back gate electrode and a second back gate electrode are arranged under the insulating layer, respectively opposite the first portion and the second portion.

Abstract: A protection device for protecting an IC against electrostatic discharge includes a buried insulant layer having a thickness that is no greater than fifty nanometers with bipolar transistors arranged thereon, one of which is NPN and the other of which is PNP. A base of one merges with a collector of the other. The transistors selectively conduct a discharge current between electrodes. A first semiconductor ground plane under the buried insulant layer is capable of being electrically biased and extends underneath the base of the first bipolar transistor. The ground plane and a base of one transistor have the same doping. However, its dopant density is at least tenfold greater than that of the base.

Abstract: A microelectronic component is capable of being used as a memory cell. The component includes a semiconductor layer resting on an insulating layer and including a doped source region of a first conductivity type, a doped drain region of a second conductivity type, and an intermediate region, non-doped or more lightly doped, with the second conductivity type, than the drain region, the intermediate region including first and second portions respectively extending from the drain region and from the source region. An insulated front gate electrode rests on the first portion. A first back gate electrode and a second back gate electrode are arranged under the insulating layer, respectively opposite the first portion and the second portion.

Abstract: A microelectronic component is capable of being used as a memory cell. The component includes a semiconductor layer resting on an insulating layer and including a doped source region of a first conductivity type, a doped drain region of a second conductivity type, and an intermediate region, non-doped or more lightly doped, with the second conductivity type, than the drain region, the intermediate region including first and second portions respectively extending from the drain region and from the source region. An insulated front gate electrode rests on the first portion. A first back gate electrode and a second back gate electrode are arranged under the insulating layer, respectively opposite the first portion and the second portion.

Abstract: A microelectronic component is capable of being used as a memory cell. The component includes a semiconductor layer resting on an insulating layer and including a doped source region of a first conductivity type, a doped drain region of a second conductivity type, and an intermediate region, non-doped or more lightly doped, with the second conductivity type, than the drain region, the intermediate region including first and second portions respectively extending from the drain region and from the source region. An insulated front gate electrode rests on the first portion. A first back gate electrode and a second back gate electrode are arranged under the insulating layer, respectively opposite the first portion and the second portion.

Abstract: A protection device for protecting an IC against electrostatic discharge includes a buried insulant layer having a thickness that is no greater than fifty nanometers with bipolar transistors arranged thereon, one of which is NPN and the other of which is PNP. A base of one merges with a collector of the other. The transistors selectively conduct a discharge current between electrodes. A first semiconductor ground plane under the buried insulant layer is capable of being electrically biased and extends underneath the base of the first bipolar transistor. The ground plane and a base of one transistor have the same doping. However, its dopant density is at least tenfold greater than that of the base.

Abstract: The invention relates to an IC with an electrostatic discharge protection device. There is a buried insulant layer 50 nm or less in thickness and first and second bipolar transistors on the insulant layer, one being an npn transistor and the other a pnp transistor. The base of the first transistor is merged with the collector of the second transistor and the base of the second transistor is merged with the collector of the first transistor. The first and second bipolar transistors are configured to selectively conduct a discharge current between two electrodes of the protection device. There is a first semiconductor ground plane under the insulant layer, being electrically biased, extending until it is plumb with the base of the first bipolar transistor, exhibiting a first type of doping identical to that of the base of the first bipolar transistor with a doping density at least ten times greater.

Abstract: The invention relates to an IC with an electrostatic discharge protection device. There is a buried insulant layer 50 nm or less in thickness and first and second bipolar transistors on the insulant layer, one being an npn transistor and the other a pnp transistor. The base of the first transistor is merged with the collector of the second transistor and the base of the second transistor is merged with the collector of the first transistor. The first and second bipolar transistors are configured to selectively conduct a discharge current between two electrodes of the protection device. There is a first semiconductor ground plane under the insulant layer, being electrically biased, extending until it is plumb with the base of the first bipolar transistor, exhibiting a first type of doping identical to that of the base of the first bipolar transistor with a doping density at least ten times greater.