Patents by Inventor Yohei Akita
Yohei Akita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9647654Abstract: A monitor circuit includes a reference voltage generating unit that generates first and second reference voltages, a first amplifier unit that amplifies a differential voltage between the first reference voltage and the second reference voltage, a second amplifier unit that amplifies a differential voltage between an internal power supply voltage being supplied to a functional block provided in the semiconductor integrated circuit and the first reference voltage, and a comparator unit that compares an amplification result of the first amplifier unit with an amplification result of the second amplifier unit and outputs a comparison result as a measurement result.Type: GrantFiled: September 11, 2015Date of Patent: May 9, 2017Assignee: Renesas Electronics CorporationInventors: Tadashi Kameyama, Takanobu Naruse, Yohei Akita, Hirotaka Hara
-
Publication number: 20160006424Abstract: A monitor circuit includes a reference voltage generating unit that generates first and second reference voltages, a first amplifier unit that amplifies a differential voltage between the first reference voltage and the second reference voltage, a second amplifier unit that amplifies a differential voltage between an internal power supply voltage being supplied to a functional block provided in the semiconductor integrated circuit and the first reference voltage, and a comparator unit that compares an amplification result of the first amplifier unit with an amplification result of the second amplifier unit and outputs a comparison result as a measurement result.Type: ApplicationFiled: September 11, 2015Publication date: January 7, 2016Inventors: Tadashi Kameyama, Takanobu Naruse, Yohei Akita, Hirotaka Hara
-
Patent number: 9146598Abstract: A monitor circuit includes a reference voltage generating unit that generates first and second reference voltages, a first amplifier unit that amplifies a differential voltage between the first reference voltage and the second reference voltage, a second amplifier unit that amplifies a differential voltage between an internal power supply voltage being supplied to a functional block provided in the semiconductor integrated circuit and the first reference voltage, and a comparator unit that compares an amplification result of the first amplifier unit with an amplification result of the second amplifier unit and outputs a comparison result as a measurement result.Type: GrantFiled: January 28, 2014Date of Patent: September 29, 2015Assignee: Renesas Electronics CorporationInventors: Tadashi Kameyama, Takanobu Naruse, Yohei Akita, Hirotaka Hara
-
Publication number: 20140210544Abstract: A monitor circuit includes a reference voltage generating unit that generates first and second reference voltages, a first amplifier unit that amplifies a differential voltage between the first reference voltage and the second reference voltage, a second amplifier unit that amplifies a differential voltage between an internal power supply voltage being supplied to a functional block provided in the semiconductor integrated circuit and the first reference voltage, and a comparator unit that compares an amplification result of the first amplifier unit with an amplification result of the second amplifier unit and outputs a comparison result as a measurement result.Type: ApplicationFiled: January 28, 2014Publication date: July 31, 2014Applicant: Renesas Mobile CorporationInventors: TADASHI KAMEYAMA, TAKANOBU NARUSE, YOHEI AKITA, HIROTAKA HARA
-
Publication number: 20090282213Abstract: A basic cell capable of a fixed operating frequency regardless of the configuration information, which is also capable of effectively utilizing the arithmetic logic circuit within the cell in a LSI semiconductor integrated circuit, is capable of dynamic changes in configuration information. The circuit has an input switch ISW connected to multiple data input nodes, an output switch OSW connected to multiple data output nodes, a first data path containing an arithmetic logic circuit ALU and a result storage flip-flop CFF0 between the input switch ISW and output switch OSW. The second data path containing a data transfer flip-flop between an input switch ISW and an output switch OSW, and the result storage flip-flop CFF stores the calculated result data from the arithmetic logic circuit ALU, and the data transfer flip-flop holds data input from any of the multiple data input nodes.Type: ApplicationFiled: July 17, 2009Publication date: November 12, 2009Inventors: Hiroshi TANAKA, Yohei Akita, Tetsuro Honmura, Fumio Arakawa, Takanobu Tsunoda
-
Patent number: 7568084Abstract: A basic cell capable of a fixed operating frequency regardless of the configuration information, which is also capable of effectively utilizing the arithmetic logic circuit within the cell in a LSI semiconductor integrated circuit, is capable of dynamic changes in configuration information. The circuit has an input switch ISW connected to multiple data input nodes, an output switch OSW connected to multiple data output nodes, a first data path containing an arithmetic logic circuit ALU and a result storage flip-flop CFF0 between the input switch ISW and output switch OSW. The second data path containing a data transfer flip-flop between an input switch ISW and an output switch OSW, and the result storage flip-flop CFF stores the calculated result data from the arithmetic logic circuit ALU, and the data transfer flip-flop holds data input from any of the multiple data input nodes.Type: GrantFiled: July 9, 2004Date of Patent: July 28, 2009Assignee: Hitachi, Ltd.Inventors: Hiroshi Tanaka, Yohei Akita, Tetsuro Honmura, Fumio Arakawa, Takanobu Tsunoda
-
Patent number: 7129741Abstract: This invention provides a storage medium on which there is stored a cell library to design a semiconductor integrated circuit to satisfy low power consumption and high speed operation and a design method using the cell library. The cell library is registered with at least two kinds of cells which are different in delay and power consumption while having the same function and the same shape. To satisfy the specification of the semiconductor integrated circuit, one cell is selected from at least two kinds of cells of the cell library.Type: GrantFiled: April 20, 2004Date of Patent: October 31, 2006Assignee: Renesas Technology Corp.Inventors: Naoki Katoh, Kazuo Yano, Yohei Akita, Mitsuru Hiraki
-
Patent number: 7039576Abstract: A system designed, including commercially distributed modules protected as intellectual property (IP), is verified in a manner that the IP provider and the user communicate with each other over a communication line to complete the system design verification. A system verification equipment to be operated by the IP provider receives from the system designer across the communication line an input vector at time n to a module provided to the system designer who designed the system integrated using one or more provided IP modules. After simulating the module operation with the input vector, the verification equipment returns an output vector obtained at time n+1 to the system designer over the communication line. The verification equipment examines the input vectors to the provided IP modules and records statistics information thereof, based on which the provider will quantitatively understand how the provided modules have been used.Type: GrantFiled: November 14, 2001Date of Patent: May 2, 2006Assignee: Renesas Technology CorporationInventor: Yohei Akita
-
Patent number: 6970017Abstract: There is provided a logic circuit causing the same delay time as a conventional logic circuit and acting as a D flip-flop circuit with a data-selecting function. A logic circuit having the circuitry shown in FIG. 6 will be described briefly. Two transmission gates TG10a (TG10b) and TG11 and two inverters IV10 and IV11 are used to define a data propagation path from an input port I1 (I2) to an output port O1. Thus, four logic gates are located along the path in the same manner as they are in a conventional D flip-flop circuit. The transmission gate TG10a (TG10b) is controlled using a NOR circuit 12a that inputs a clock CLK and a select signal /sel that is the reverse of a select signal sel (NOR circuit 12b that inputs the clock CLK and the select signal sel). The transmission gate TG11 is controlled with the clock CLK. Either of two input data items is selected based on the select signals, and then output.Type: GrantFiled: September 6, 2001Date of Patent: November 29, 2005Assignee: Renesas Technology Corp.Inventors: Yohei Akita, Naoki Kato, Kazuo Yano
-
Publication number: 20050015572Abstract: A basic cell capable of a fixed operating frequency regardless of the configuration information, which is also capable of effectively utilizing the arithmetic logic circuit within the cell in a LSI semiconductor integrated circuit, is capable of dynamic changes in configuration information. The circuit has an input switch ISW connected to multiple data input nodes, an output switch OSW connected to multiple data output nodes, a first data path containing an arithmetic logic circuit ALU and a result storage flip-flop CFF0 between the input switch ISW and output switch OSW. The second data path containing a data transfer flip-flop between an input switch ISW and an output switch OSW, and the result storage flip-flop CFF stores the calculated result data from the arithmetic logic circuit ALU, and the data transfer flip-flop holds data input from any of the multiple data input nodes.Type: ApplicationFiled: July 9, 2004Publication date: January 20, 2005Inventors: Hiroshi Tanaka, Yohei Akita, Tetsuro Honmura, Fumio Arakawa, Takanobu Tsunoda
-
Publication number: 20040236929Abstract: The present invention provides a program which can maintain program compatibility between different hardware in a small hardware quantity and realize high performance scalability. An operation to be executed and an execution order limitation (dependency) for executing the operation are described into a program given to a logic circuit (hardware) having an ALU and a control circuit. The control circuit in the logic circuit decides an operation execution order based on the dependency described into the read program.Type: ApplicationFiled: March 3, 2004Publication date: November 25, 2004Inventor: Yohei Akita
-
Publication number: 20040196684Abstract: This invention provides a storage medium on which there is stored a cell library to design a semiconductor integrated circuit to satisfy low power consumption and high speed operation and a design method using the cell library. The cell library is registered with at least two kinds of cells which are different in delay and power consumption while having the same function and the same shape. To satisfy the specification of the semiconductor integrated circuit, one cell is selected from at least two kinds of cells of the cell library.Type: ApplicationFiled: April 20, 2004Publication date: October 7, 2004Applicant: Renesas Technology Corp.Inventors: Naoki Katoh, Kazuo Yano, Yohei Akita, Mitsuru Hiraki
-
Patent number: 6769110Abstract: This invention provides a storage medium on which there is stored a cell library to design a semiconductor integrated circuit to satisfy low power consumption and high speed operation and a design method using the cell library. The cell library is registered with at least two kinds of cells which are different in delay and power consumption while having the same function and the same shape. To satisfy the specification of the semiconductor integrated circuit, one cell is selected from at least two kinds of cells of the cell library.Type: GrantFiled: February 28, 2002Date of Patent: July 27, 2004Assignee: Renesas Technology Corp.Inventors: Naoki Katoh, Kazuo Yano, Yohei Akita, Mitsuru Hiraki
-
Publication number: 20020079927Abstract: Disclosed is a semiconductor integrated circuit device constructed of MOSFETs in which there is attained a harmony between increase in consumption power due to a leakage current and operating speed of the MOSFETs in a suitable manner, and among a plurality of signal paths in the semiconductor integrated circuit device, a path which has a margin in delay is constructed with MOSFETs each with a high threshold voltage, while a path which has no margin in delay is constructed with MOSFETs each with a low threshold voltage which has a large leakage current but a high operating speed, in light of a delay with which a signal is transmitted along a signal path.Type: ApplicationFiled: February 28, 2002Publication date: June 27, 2002Applicant: Hitachi Ltd.Inventors: Naoki Katoh, Kazuo Yano, Yohei Akita, Mitsuru Hiraki
-
Publication number: 20020059053Abstract: A system designed, including commercially distributed modules protected as intellectual property (IP), is verified in a manner that the IP provider and the user communicate with each other over a communication line to complete the system design verification. A system verification equipment to be operated by the IP provider receives from the system designer across the communication line an input vector at time n to a module provided to the system designer who designed the system integrated using one or more provided IP modules. After simulating the module operation with the input vector, the verification equipment returns an output vector obtained at time n+1 to the system designer over the communication line. The verification equipment examines the input vectors to the provided IP modules and records statistics information thereof, based on which the provider will quantitatively understand how the provided modules have been used.Type: ApplicationFiled: November 14, 2001Publication date: May 16, 2002Inventor: Yohei Akita
-
Patent number: 6380764Abstract: Disclosed is a semiconductor integrated circuit device constructed of MOSFETs in which there is attained a harmony between increase in consumption power due to a leakage current and operating speed of the MOSFETs in a suitable manner, and among a plurality of signal paths in the semiconductor integrated circuit device, a path which has a margin in delay is constructed with MOSFETs each with a high threshold voltage, while a path which has no margin in delay is constructed with MOSFETs each with a low threshold voltage which has a large leakage current but a high operating speed, in light of a delay with which a signal is transmitted along a signal path.Type: GrantFiled: June 23, 2000Date of Patent: April 30, 2002Assignee: Hitachi, Ltd.Inventors: Naoki Katoh, Kazuo Yano, Yohei Akita, Mitsuru Hiraki
-
Publication number: 20020043990Abstract: There is provided a logic circuit causing the same delay time as a conventional logic circuit and acting as a D flip-flop circuit with a data-selecting function.Type: ApplicationFiled: September 6, 2001Publication date: April 18, 2002Applicant: Hitachi, Ltd.Inventors: Yohei Akita, Naoki Kato, Kazuo Yano
-
Patent number: 6320421Abstract: There is provided a logic circuit causing the same delay time as a conventional logic circuit and acting as a D flip-flop circuit with a data-selecting function. A logic circuit having the circuitry shown in FIG. 6 will be described briefly. Two transmission gates TG10a (TG10b) and TG11 and two inverters IV10 and IV11 are used to define a data propagation path from an input port I1 (I2) to an output port O1. Thus, four logic gates are located along the path in the same manner as they are in a conventional D flip-flop circuit. The transmission gate TG10a (TG10b) is controlled using a NOR circuit 12a that inputs a clock CLK and a select signal /sel that is the reverse of a select signal sel (NOR circuit 12b that inputs the clock CLK and the select signal sel). The transmission gate TG11 is controlled with the clock CLK. Either of two input data items is selected based on the select signals, and then output.Type: GrantFiled: May 30, 2000Date of Patent: November 20, 2001Assignee: Hitachi, Ltd.Inventors: Yohei Akita, Naoki Kato, Kazuo Yano