Patents by Inventor Yohji Watanabe
Yohji Watanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8027216Abstract: A memory may includes: word lines; bit lines; memory array blocks including memory cells, each memory array block being a unit of a data read operation or a data write operation; a row decoder configured to selectively drive the word lines; sense amplifiers configured to detect data; and an access counter provided for each memory cell block, the access counter counting the number of times of accessing the memory array blocks in order to read data or write data, and activating a refresh request signal when the number of times of access reaches a predetermined number of times, wherein during an activation period of the refresh request signal of the access counter, the row decoder periodically and sequentially activates the word lines of the memory array blocks corresponding to the access counter, and the sense amplifier performs a refresh operation of the memory cells connected to the activated word lines.Type: GrantFiled: August 31, 2009Date of Patent: September 27, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Ryo Fukuda, Yohji Watanabe
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Patent number: 7888769Abstract: A semiconductor integrated circuit device according to an embodiment of the present invention includes: a semiconductor substrate; an internal circuit formed on the semiconductor substrate, a first potential and a second potential being supplied to the internal circuit, thereby applying an operating voltage to the internal circuit; a fuse disposed above a semiconductor region of a first conductivity type, and electrically connected to the internal circuit, the semiconductor region being supplied with the second potential and being formed in the semiconductor substrate; and a protective element formed in the semiconductor region of the first conductivity type and protecting the internal circuit in response to positive and negative abnormal voltages generated in a wiring through which the fuse and the internal circuit are connected to each other.Type: GrantFiled: May 31, 2007Date of Patent: February 15, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Masaki Kondo, Ryo Fukuda, Yohji Watanabe, Mitsutoshi Nakamura
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Patent number: 7732840Abstract: A second-conductivity-type transistor includes a source and drain formed by a second-conductivity-type diffusion layer formed on a first-conductivity-type semiconductor layer; and a gate formed on the first-conductivity-type semiconductor layer sandwiched between the second-conductivity-type diffusion layer through an insulating film A first-conductivity-type transistor includes a source and drain formed by a first-conductivity-type diffusion layer formed on a second-conductivity-type semiconductor layer; and a gate formed on the second-conductivity-type semiconductor layer sandwiched between the first-conductivity-type diffusion layer through an insulating film. The second-conductivity-type diffusion layer for configuring the second-conductivity-type transistor is divided into a plurality of regions, each of which being separated by a device isolation region formed on the first-conductivity-type semiconductor layer.Type: GrantFiled: September 28, 2007Date of Patent: June 8, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Fumiyoshi Matsuoka, Yohji Watanabe, Ryo Fukuda
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Publication number: 20100074042Abstract: A memory may includes: word lines; bit lines; memory array blocks including memory cells, each memory array block being a unit of a data read operation or a data write operation; a row decoder configured to selectively drive the word lines; sense amplifiers configured to detect data; and an access counter provided for each memory cell block, the access counter counting the number of times of accessing the memory array blocks in order to read data or write data, and activating a refresh request signal when the number of times of access reaches a predetermined number of times, wherein during an activation period of the refresh request signal of the access counter, the row decoder periodically and sequentially activates the word lines of the memory array blocks corresponding to the access counter, and the sense amplifier performs a refresh operation of the memory cells connected to the activated word lines.Type: ApplicationFiled: August 31, 2009Publication date: March 25, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Ryo FUKUDA, Yohji Watanabe
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Publication number: 20080079473Abstract: A second-conductivity-type transistor includes a source and drain formed by a second-conductivity-type diffusion layer formed on a first-conductivity-type semiconductor layer; and a gate formed on the first-conductivity-type semiconductor layer sandwiched between the second-conductivity-type diffusion layer through an insulating film A first-conductivity-type transistor includes a source and drain formed by a first-conductivity-type diffusion layer formed on a second-conductivity-type semiconductor layer; and a gate formed on the second-conductivity-type semiconductor layer sandwiched between the first-conductivity-type diffusion layer through an insulating film. The second-conductivity-type diffusion layer for configuring the second-conductivity-type transistor is divided into a plurality of regions, each of which being separated by a device isolation region formed on the first-conductivity-type semiconductor layer.Type: ApplicationFiled: September 28, 2007Publication date: April 3, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Fumiyoshi Matsuoka, Yohji Watanabe, Ryo Fukuda
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Publication number: 20070278580Abstract: A semiconductor integrated circuit device according to an embodiment of the present invention includes: a semiconductor substrate; an internal circuit formed on the semiconductor substrate, a first potential and a second potential being supplied to the internal circuit, thereby applying an operating voltage to the internal circuit; a fuse disposed above a semiconductor region of a first conductivity type, and electrically connected to the internal circuit, the semiconductor region being supplied with the second potential and being formed in the semiconductor substrate; and a protective element formed in the semiconductor region of the first conductivity type and protecting the internal circuit in response to positive and negative abnormal voltages generated in a wiring through which the fuse and the internal circuit are connected to each other.Type: ApplicationFiled: May 31, 2007Publication date: December 6, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Masaki KONDO, Ryo Fukuda, Yohji Watanabe, Mitsutoshi Nakamura
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Patent number: 7218560Abstract: A semiconductor memory device includes a fuse element including a first terminal and a second terminal, which stores data based on whether or not it is electrically blown by a laser beam, a resistance element connected to the first terminal, a node in which the data is transferred, and a transistor provided between the resistance element and the node, which sets the data to the node.Type: GrantFiled: December 5, 2005Date of Patent: May 15, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Ryo Fukuda, Yohji Watanabe, Shuso Fujii
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Patent number: 7079432Abstract: A semiconductor storage device has a function of simultaneously activating a plurality of word lines connected to the same bit line via cell transistors. The semiconductor storage device comprises a column redundancy system that sets repair regions of column redundancy based on row addresses. By the column redundancy system, the repair regions are set to cause the plurality of word lines which can be activated together to belong to the same repair region, when the repair regions are set to divide the bit line.Type: GrantFiled: January 20, 2005Date of Patent: July 18, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Daisuke Kato, Takashi Taira, Kenji Ishizuka, Yohji Watanabe, Munehiro Yoshida
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Publication number: 20060119415Abstract: A semiconductor memory device includes a fuse element including a first terminal and a second terminal, which stores data based on whether or not it is electrically blown by a laser beam, a resistance element connected to the first terminal, a node in which the data is transferred, and a transistor provided between the resistance element and the node, which sets the data to the node.Type: ApplicationFiled: December 5, 2005Publication date: June 8, 2006Inventors: Ryo Fukuda, Yohji Watanabe, Shuso Fujii
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Publication number: 20050122802Abstract: There is provided a semiconductor storage device in which only a defective element is replaced by a row redundant element to compensate for a defect if at least one of a plurality of elements is defective in a case where the plurality of elements in a memory cell array are simultaneously activated. The semiconductor storage device includes an array control circuit which is configured to interrupt the operation of the defective element by preventing a word line state signal from being received based on a signal to determine whether a row redundancy replacement process is performed or not. The word line state signal is input to the plurality of memory blocks in the cell array unit via a single signal line.Type: ApplicationFiled: January 20, 2005Publication date: June 9, 2005Inventors: Daisuke Kato, Takashi Taira, Kenji Ishizuka, Yohji Watanabe, Munehiro Yoshida
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Patent number: 6876588Abstract: There is provided a semiconductor storage device in which only a defective element is replaced by a row redundant element to compensate for a defect if at least one of a plurality of elements is defective in a case where the plurality of elements in a memory cell array are simultaneously activated. The semiconductor storage device includes an array control circuit which is configured to interrupt the operation of the defective element by preventing a word line state signal from being received based on a signal to determine whether a row redundancy replacement process is performed or not. The word line state signal is input to the plurality of memory blocks in the cell array unit via a single signal line.Type: GrantFiled: September 17, 2003Date of Patent: April 5, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Daisuke Kato, Takashi Taira, Kenji Ishizuka, Yohji Watanabe, Munehiro Yoshida
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Patent number: 6856561Abstract: A semiconductor memory device has a cell array, first normal elements each defined within the cell array as a group of memory cells arranged in a first direction of the cell array, second normal elements each defined within the cell array as a group of memory cells arranged in a second direction of the cell array, each the second normal element selecting a memory cells in operative association with a corresponding one of the first normal elements, first redundant elements disposed for replacement of defective first normal elements within the cell array, and second redundant elements disposed for replacement of defective second normal elements within the cell array. There are defined within the cell array first/second repair regions as a group of first/second normal elements with permission of replacement by each first/second redundant element.Type: GrantFiled: September 8, 2003Date of Patent: February 15, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Daisuke Kato, Munehiro Yoshida, Yohji Watanabe
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Patent number: 6834016Abstract: A semiconductor memory device having a memory system and a redundancy system including redundant elements for repairing a plurality of defects in the memory system, comprising a plurality of address fuse sets each including address fuses for programming a defective address in the memory system, and a master fuse for preventing a corresponding redundant element from being selected when the redundant element is not used, wherein at least one master fuse is shared by at least two fuse sets among the plurality of address fuse sets.Type: GrantFiled: April 23, 2003Date of Patent: December 21, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Daisuke Kato, Yohji Watanabe
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Patent number: 6741509Abstract: There is provided a semiconductor storage device in which only a defective element is replaced by a row redundant element to compensate for a defect if at least one of a plurality of elements is defective in a case where the plurality of elements in a memory cell array are simultaneously activated. The semiconductor storage device includes an array control circuit which is configured to interrupt the operation of the defective element by preventing a word line state signal from being received based on a signal to determine whether a row redundancy replacement process is performed or not. The word line state signal is input to the plurality of memory blocks in the cell array unit via a single signal line.Type: GrantFiled: January 16, 2002Date of Patent: May 25, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Daisuke Kato, Takashi Taira, Kenji Ishizuka, Yohji Watanabe
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Publication number: 20040062134Abstract: There is provided a semiconductor storage device in which only a defective element is replaced by a row redundant element to compensate for a defect if at least one of a plurality of elements is defective in a case where the plurality of elements in a memory cell array are simultaneously activated. The semiconductor storage device includes an array control circuit which is configured to interrupt the operation of the defective element by preventing a word line state signal from being received based on a signal to determine whether a row redundancy replacement process is performed or not. The word line state signal is input to the plurality of memory blocks in the cell array unit via a single signal line.Type: ApplicationFiled: September 17, 2003Publication date: April 1, 2004Applicant: KABUSHIKI KAISHA TOSHIBA.Inventors: Daisuke Kato, Takashi Taira, Kenji Ishizuka, Yohji Watanabe, Munehiro Yoshida
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Publication number: 20040057309Abstract: A semiconductor memory device has a cell array, first normal elements each defined within the cell array as a group of memory cells arranged in a first direction of the cell array, second normal elements each defined within the cell array as a group of memory cells arranged in a second direction of the cell array, each the second normal element selecting a memory cells in operative association with a corresponding one of the first normal elements, first redundant elements disposed for replacement of defective first normal elements within the cell array, and second redundant elements disposed for replacement of defective second normal elements within the cell array. There are defined within the cell array a first repair regions as a group of first normal elements with permission of replacement by each first redundant element and second repair regions defined within the cell array as a group of second normal elements with permission of replacement by each second redundant element.Type: ApplicationFiled: September 8, 2003Publication date: March 25, 2004Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Daisuke Kato, Munehiro Yoshida, Yohji Watanabe
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Patent number: 6711648Abstract: The present invention includes a cost efficient method of substantially increasing the data bandwidth of a dynamic random access memory (DRAM) device initially configured to operate in an extended data output (EDO) mode, the EDO DRAM device including at least one storage cell, a column decoder, an internal read/write data bus and an off chip driver latch, the column decoder decoding a column address upon receipt thereof such that data stored in the at least one storage cell corresponding to the decoded column addresses is placed on the internal read/write data bus in response to the receipt of an address transition detection (ATD) pulse generated by the dynamic memory device and further wherein output data is stored in the off chip driver latch in response to a transfer pulse.Type: GrantFiled: March 28, 1997Date of Patent: March 23, 2004Assignee: Siemens Aktiengesellschaft Kabushiki Kaisha ToshibaInventors: Peter Poechmueller, Yohji Watanabe
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Patent number: 6646932Abstract: A semiconductor memory device has a cell array, first normal elements each defined within the cell array as a group of memory cells arranged in a first direction of the cell array, second normal elements each defined within the cell array as a group of memory cells arranged in a second direction of the cell array, each the second normal element selecting a memory cells in operative association with a corresponding one of the first normal elements, first redundant elements disposed for replacement of defective first normal elements within the cell array, and second redundant elements disposed for replacement of defective second normal elements within the cell array. There are defined within the cell array first/second repair region as group of first/second normal elements with permission of replacement by each first/second redundant element.Type: GrantFiled: June 3, 2002Date of Patent: November 11, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Daisuke Kato, Munehiro Yoshida, Yohji Watanabe
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Publication number: 20030206452Abstract: A semiconductor memory device having a memory system and a redundancy system including redundant elements for repairing a plurality of defects in the memory system, comprising a plurality of address fuse sets each including address fuses for programming a defective address in the memory system, and a master fuse for preventing a corresponding redundant element from being selected when the redundant element is not used, wherein at least one master fuse is shared by at least two fuse sets among the plurality of address fuse sets.Type: ApplicationFiled: April 23, 2003Publication date: November 6, 2003Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Daisuke Kato, Yohji Watanabe
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Patent number: 6603689Abstract: A semiconductor memory device having a memory system and a redundancy system including redundant elements for repairing a plurality of defects in the memory system, comprising a plurality of address fuse sets each including address fuses for programming a defective address in the memory system, and a master fuse for preventing a corresponding redundant element from being selected when the redundant element is not used, wherein at least one master fuse is shared by at least two fuse sets among the plurality of address fuse sets.Type: GrantFiled: January 11, 2002Date of Patent: August 5, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Daisuke Kato, Yohji Watanabe