Patents by Inventor Yohsuke Inoue

Yohsuke Inoue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6462411
    Abstract: A semiconductor wafer processing apparatus comprises a reaction furnace capable of heating inside thereof, a wafer mount for mounting a semiconductor wafer thereon and a transfer device. The wafermount includes an opening which is greater than the semiconductor wafer and which has a circle shape or a shape substantially similar to an outer periphery of the semiconductor wafer, and includes a wafer supporting portion projecting inwardly of the opening for supporting the semiconductor wafer. The transfer device is capable of holding the wafer mount outside the semiconductor wafer as viewed from a vertical direction, and transferring the wafer mount carrying the semiconductor wafer thereon substantially horizontally into and/or out from the reaction furnace.
    Type: Grant
    Filed: December 4, 1998
    Date of Patent: October 8, 2002
    Assignee: Kokusai Electric Co., LTD
    Inventors: Tomoji Watanabe, Nobuyuki Mise, Toshiyuki Uchino, Norio Suzuki, Yoshihiko Sakurai, Toshiya Uenishi, Yohsuke Inoue, Yasuhiro Inokuchi, Fumihide Ikeda
  • Patent number: 6283273
    Abstract: A substrate processing apparatus comprises a substrate processing chamber, a transfer chamber, a substrate mounting body having a through hole formed in a vertical direction and being provided in the substrate processing chamber, a substrate lifting member capable of vertically moving in the through hole, a first arm, capable of extending from the transfer chamber into the substrate processing chamber, for transferring the substrate in a horizontal direction, a second arm capable of extending from the transfer chamber into the substrate processing chamber, capable of moving in a vertical direction and separating the substrate upward from the substrate mounting body by moving the substrate lifting member upward, and a driving mechanism provided in the transfer chamber for extending the first and second arms from the transfer chamber into the substrate processing chamber and for moving the first arm in the horizontal direction and moving the second arm in the vertical direction.
    Type: Grant
    Filed: December 8, 1999
    Date of Patent: September 4, 2001
    Assignee: Kokusai Electric Co., Ltd.
    Inventors: Akihiro Miyauchi, Yohsuke Inoue, Takaya Suzuki
  • Patent number: 5736753
    Abstract: To provide a field-effect transistor having a large power conversion capacity and its fabrication method by decreasing the leakage current between the source and the drain of a semiconductor device made of hexagonal-system silicon carbide when the gate voltage of the semiconductor device is turned off and also decreasing the electrical resistance of the semiconductor device when the gate voltage of the semiconductor device is turned on. The main current path of the field-effect transistor is formed so that the current flowing between the source and the drain of, for example, a field-effect transistor flows in the direction parallel with the {0001} plane and a channel forming plane is parallel with the {1120} plane. ?Selected Drawing!FIG.
    Type: Grant
    Filed: August 30, 1995
    Date of Patent: April 7, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Toshiyuki Ohno, Yohsuke Inoue, Daisuke Kawase, Yuzo Kozono, Takaya Suzuki, Tsutomu Yatsuo
  • Patent number: 5233216
    Abstract: A dielectric isolated substrate wherein a connecting polycrystalline silicon layer has smooth and flat surface on which a single crystal support is bonded and has a densified crystal structure, or is obtained by further heat treatment at 800.degree. C. or higher after deposition, or has no orientation as to growth direction of polycrystalline silicon, or a buffering layer is formed between a polycrystalline silicon layer and a single crystal support, is excellent in bonding between the single crystal support and the polycrystalline silicon layer by preventing voids at the bonded surface, while enhancing reliability.
    Type: Grant
    Filed: October 19, 1992
    Date of Patent: August 3, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Yohsuke Inoue, Michio Ohue, Saburoo Ogawa, Kiyoshi Thukuda, Takeshi Tanaka, Yasuhiro Mochizuki