Patents by Inventor Yoichi Otani
Yoichi Otani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140370665Abstract: A method for manufacturing a power semiconductor device is disclosed which can include: providing a wafer of a first conductivity type; and applying on a second main side of the wafer at least one of a dopant of the first conductivity type for forming a layer of the first conductivity type and a dopant of a second conductivity type for forming a layer of the second conductivity type. A Titanium layer with a metal having a melting point above 1300° C. is then deposited on the second main side. The Titanium deposition layer is annealed so that simultaneously an intermetal compound layer is formed at the interface between the Titanium deposition layer and the wafer and the dopant is diffused into the wafer. A first metal electrode layer is created on the second main side.Type: ApplicationFiled: September 4, 2014Publication date: December 18, 2014Applicant: ABB Technology AGInventors: Munaf RAHIMO, Chiara Corvasce, Jan Vobecky, Yoichi Otani
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Patent number: 8513779Abstract: The present invention relates to complementary devices, such as n-FETs and p-FETs, which have hybrid channel orientations and are connected by conductive connectors that are embedded in a semiconductor substrate. Specifically, the semiconductor substrate has at least first and second device regions of different surface crystal orientations (i.e., hybrid orientations). An n-FET is formed at one of the first and second device regions, and a p-FET is formed at the other of the first and second device regions. The n-FET and the p-FET are electrically connected by a conductive connector that is located between the first and second device regions and embedded in the semiconductor substrate. Preferably, a dielectric spacer is first provided between the first and second device regions and recessed to form a gap therebetween. The conductive connector is then formed in the gap above the recessed dielectric spacer.Type: GrantFiled: July 27, 2012Date of Patent: August 20, 2013Assignee: International Business Machines CorporationInventors: Byeong Y. Kim, Xiaomeng Chen, Yoichi Otani
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Publication number: 20120292668Abstract: The present invention relates to complementary devices, such as n-FETs and p-FETs, which have hybrid channel orientations and are connected by conductive connectors that are embedded in a semiconductor substrate. Specifically, the semiconductor substrate has at least first and second device regions of different surface crystal orientations (i.e., hybrid orientations). An n-FET is formed at one of the first and second device regions, and a p-FET is formed at the other of the first and second device regions. The n-FET and the p-FET are electrically connected by a conductive connector that is located between the first and second device regions and embedded in the semiconductor substrate. Preferably, a dielectric spacer is first provided between the first and second device regions and recessed to form a gap therebetween. The conductive connector is then formed in the gap above the recessed dielectric spacer.Type: ApplicationFiled: July 27, 2012Publication date: November 22, 2012Applicant: International Business Machines CorporationInventors: Byeong Y. Kim, Xiaomeng Chen, Yoichi Otani
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Patent number: 8237247Abstract: The present invention relates to complementary devices, such as n-FETs and p-FETs, which have hybrid channel orientations and are connected by conductive connectors that are embedded in a semiconductor substrate. Specifically, the semiconductor substrate has at least first and second device regions of different surface crystal orientations (i.e., hybrid orientations). An n-FET is formed at one of the first and second device regions, and a p-FET is formed at the other of the first and second device regions. The n-FET and the p-FET are electrically connected by a conductive connector that is located between the first and second device regions and embedded in the semiconductor substrate. Preferably, a dielectric spacer is first provided between the first and second device regions and recessed to form a gap therebetween. The conductive connector is then formed in the gap above the recessed dielectric spacer.Type: GrantFiled: September 8, 2009Date of Patent: August 7, 2012Assignee: International Business Machines CorporationInventors: Byeong Y. Kim, Xiaomeng Chen, Yoichi Otani
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Patent number: 8120095Abstract: The present invention provides two-transistor silicon-oxide-nitride-oxide-semiconductor (2-Tr SONOS) non-volatile memory cells with randomly accessible storage locations as well as a design structure including the semiconductor memory devices embodied in a machine readable medium. In one embodiment, a 2-Tr SONOS cell is provided in which the select transistor is located with a trench structure having trench depth from 1 to 2 ?m and the memory transistor is located on a surface of a semiconductor substrate adjoining the trench structure. In another embodiment, a 2-Tr SONOS memory cell is provided in which both the select transistor and the memory transistor are located within a trench structure having the depth mentioned above.Type: GrantFiled: December 13, 2007Date of Patent: February 21, 2012Assignee: International Business Machines CorporationInventors: Herbert L. Ho, Jack A. Mandelman, Tak H. Ning, Yoichi Otani
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Patent number: 8008713Abstract: A semiconductor memory device in which a vertical trench semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell is created in a semiconductor-on-insulator (SOI) substrate is provided that allows for the integration of dense non-volatile random access memory (NVRAM) cells in SOI-based complementary metal oxide semiconductor (CMOS) technology. The trench is processed using conventional trench processing and it is processed near the beginning of the inventive method that allows for the fabrication of the memory cell to be fully separated from SOI logic processing.Type: GrantFiled: March 25, 2009Date of Patent: August 30, 2011Assignee: International Business Machines CorporationInventors: David M. Dobuzinsky, Herbert L. Ho, Jack A. Mandelman, Yoichi Otani
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Patent number: 7893485Abstract: A semiconductor memory device and a design structure including the semiconductor memory device embodied in a machine readable medium is provided. In particular the present invention includes a semiconductor memory device in which a vertical trench semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell is created in a semiconductor-on-insulator (SOI) substrate is provided that allows for the integration of dense non-volatile random access memory (NVRAM) cells in SOI-based complementary metal oxide semiconductor (CMOS) technology. The trench is processed using conventional trench processing and it is processed near the beginning of the inventive method that allows for the fabrication of the memory cell to be fully separated from SOI logic processing.Type: GrantFiled: December 13, 2007Date of Patent: February 22, 2011Assignee: International Business Machines CorporationInventors: David M. Dobuzinsky, Herbert L. Ho, Jack A. Mandelman, Yoichi Otani
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Patent number: 7816728Abstract: The present invention provides two-transistor silicon-oxide-nitride-oxide-semiconductor (2-Tr SONOS) non-volatile memory cells with randomly accessible storage locations as well as method of fabricating the same. In one embodiment, a 2-Tr SONOS cell is provided in which the select transistor is located within a trench structure having trench depth from 1 to 2 ?m and the memory transistor is located on a surface of a semiconductor substrate adjoining the trench structure. In another embodiment, a 2-Tr SONOS memory cell is provided in which both the select transistor and the memory transistor are located within a trench structure having the depth mentioned above.Type: GrantFiled: April 12, 2005Date of Patent: October 19, 2010Assignee: International Business Machines CorporationInventors: Herbert L. Ho, Jack A. Mandelman, Tak H. Ning, Yoichi Otani
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Patent number: 7807526Abstract: The present invention provides two-transistor silicon-oxide-nitride-oxide-semiconductor (2-Tr SONOS) non-volatile memory cells with randomly accessible storage locations as well as method of fabricating the same. In one embodiment, a 2-Tr SONOS cell is provided in which the select transistor is located with a trench structure having trench depth from 1 to 2 ?m and the memory transistor is located on a surface of a semiconductor substrate adjoining the trench structure. In another embodiment, a 2-Tr SONOS memory cell is provided in which both the select transistor and the memory transistor are located within a trench structure having the depth mentioned above.Type: GrantFiled: October 30, 2007Date of Patent: October 5, 2010Assignee: International Business Machines CorporationInventors: Herbert L. Ho, Jack A. Mandelman, Tak H. Ning, Yoichi Otani
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Publication number: 20090321794Abstract: The present invention relates to complementary devices, such as n-FETs and p-FETs, which have hybrid channel orientations and are connected by conductive connectors that are embedded in a semiconductor substrate. Specifically, the semiconductor substrate has at least first and second device regions of different surface crystal orientations (i.e., hybrid orientations). An n-FET is formed at one of the first and second device regions, and a p-FET is formed at the other of the first and second device regions. The n-FET and the p-FET are electrically connected by a conductive connector that is located between the first and second device regions and embedded in the semiconductor substrate. Preferably, a dielectric spacer is first provided between the first and second device regions and recessed to form a gap therebetween. The conductive connector is then formed in the gap above the recessed dielectric spacer.Type: ApplicationFiled: September 8, 2009Publication date: December 31, 2009Applicant: International Business Machines CorporationInventors: Byeong Y. Kim, Xiaomeng Chen, Yoichi Otani
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Patent number: 7595232Abstract: The present invention relates to complementary devices, such as n-FETs and p-FETs, which have hybrid channel orientations and are connected by conductive connectors that are embedded in a semiconductor substrate. Specifically, the semiconductor substrate has at least first and second device regions of different surface crystal orientations (i.e., hybrid orientations). An n-FET is formed at one of the first and second device regions, and a p-FET is formed at the other of the first and second device regions. The n-FET and the p-FET are electrically connected by a conductive connector that is located between the first and second device regions and embedded in the semiconductor substrate. Preferably, a dielectric spacer is first provided between the first and second device regions and recessed to form a gap therebetween. The conductive connector is then formed in the gap above the recessed dielectric spacer.Type: GrantFiled: September 7, 2006Date of Patent: September 29, 2009Assignee: International Business Machines CorporationInventors: Byeong Y. Kim, Xiaomeng Chen, Yoichi Otani
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Publication number: 20090224308Abstract: A semiconductor memory device in which a vertical trench semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell is created in a semiconductor-on-insulator (SOI) substrate is provided that allows for the integration of dense non-volatile random access memory (NVRAM) cells in SOI-based complementary metal oxide semiconductor (CMOS) technology. The trench is processed using conventional trench processing and it is processed near the beginning of the inventive method that allows for the fabrication of the memory cell to be fully separated from SOI logic processing.Type: ApplicationFiled: March 25, 2009Publication date: September 10, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David M. Dobuzinsky, Herbert L. Ho, Jack A. Mandelman, Yoichi Otani
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Patent number: 7575970Abstract: Methods of forming a deep trench capacitor through an SOI substrate, and a capacitor are disclosed. In one embodiment, a method includes forming a trench opening into the SOI substrate to the silicon substrate; depositing a sidewall spacer in the trench opening; etching to form the deep trench into the silicon substrate; forming a first electrode by implanting a dopant into the silicon substrate, whereby the sidewall spacer protects the BOX layer and the silicon layer; removing the sidewall spacer; depositing a node dielectric within the deep trench; and forming a second electrode by depositing a conductor in the deep trench. Implanting creates a substantially uniform depth doped region except at a portion adjacent to a lowermost portion of the deep trench, which may be substantially bulbous. The BOX layer is protected from undercutting by the sidewall spacer, and the implantation removes the need for out-diffusing dopant from silica glass.Type: GrantFiled: September 7, 2006Date of Patent: August 18, 2009Assignee: International Business Machines CorporationInventors: Herbert L. Ho, Kangguo Cheng, Yoichi Otani, Kevin R. Winstel
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Publication number: 20090158234Abstract: A semiconductor memory device and a design structure including the semiconductor memory device embodied in a machine readable medium is provided. In particular the present invention includes a semiconductor memory device in which a vertical trench semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell is created in a semiconductor-on-insulator (SOI) substrate is provided that allows for the integration of dense non-volatile random access memory (NVRAM) cells in SOI-based complementary metal oxide semiconductor (CMOS) technology. The trench is processed using conventional trench processing and it is processed near the beginning of the inventive method that allows for the fabrication of the memory cell to be fully separated from SOI logic processing.Type: ApplicationFiled: December 13, 2007Publication date: June 18, 2009Applicant: INTERNATIONAL MACHINES BUSINESS CORPORATIONInventors: David M. Dobuzinsky, Herbert L. Ho, Jack A. Mandelman, Yoichi Otani
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Publication number: 20090158226Abstract: The present invention provides two-transistor silicon-oxide-nitride-oxide-semiconductor (2-Tr SONOS) non-volatile memory cells with randomly accessible storage locations as well as a design structure including the semiconductor memory devices embodied in a machine readable medium. In one embodiment, a 2-Tr SONOS cell is provided in which the select transistor is located with a trench structure having trench depth from 1 to 2 ?m and the memory transistor is located on a surface of a semiconductor substrate adjoining the trench structure. In another embodiment, a 2-Tr SONOS memory cell is provided in which both the select transistor and the memory transistor are located within a trench structure having the depth mentioned above.Type: ApplicationFiled: December 13, 2007Publication date: June 18, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Herbert L. Ho, Jack A. Mandelman, Tak H. Ning, Yoichi Otani
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Patent number: 7514323Abstract: A semiconductor memory device in which a vertical trench semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell is created in a semiconductor-on-insulator (SOI) substrate is provided that allows for the integration of dense non-volatile random access memory (NVRAM) cells in SOI-based complementary metal oxide semiconductor (CMOS) technology. The trench is processed using conventional trench processing and it is processed near the beginning of the inventive method that allows for the fabrication of the memory cell to be fully separated from SOI logic processing.Type: GrantFiled: November 28, 2005Date of Patent: April 7, 2009Assignee: International Business Machines CorporationInventors: David M. Dobuzinsky, Herbert L. Ho, Jack A. Mandelman, Yoichi Otani
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Publication number: 20080064178Abstract: Methods of forming a deep trench capacitor through an SOI substrate, and a capacitor are disclosed. In one embodiment, a method includes forming a trench opening into the SOI substrate to the silicon substrate; depositing a sidewall spacer in the trench opening; etching to form the deep trench into the silicon substrate; forming a first electrode by implanting a dopant into the silicon substrate, whereby the sidewall spacer protects the BOX layer and the silicon layer; removing the sidewall spacer; depositing a node dielectric within the deep trench; and forming a second electrode by depositing a conductor in the deep trench. Implanting creates a substantially uniform depth doped region except at a portion adjacent to a lowermost portion of the deep trench, which may be substantially bulbous. The BOX layer is protected from undercutting by the sidewall spacer, and the implantation removes the need for out-diffusing dopant from silica glass.Type: ApplicationFiled: September 7, 2006Publication date: March 13, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Herbert L. Ho, Kangguo Cheng, Yoichi Otani, Kevin R. Winstel
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Publication number: 20080064160Abstract: The present invention relates to complementary devices, such as n-FETs and p-FETs, which have hybrid channel orientations and are connected by conductive connectors that are embedded in a semiconductor substrate. Specifically, the semiconductor substrate has at least first and second device regions of different surface crystal orientations (i.e., hybrid orientations). An n-FET is formed at one of the first and second device regions, and a p-FET is formed at the other of the first and second device regions. The n-FET and the p-FET are electrically connected by a conductive connector that is located between the first and second device regions and embedded in the semiconductor substrate. Preferably, a dielectric spacer is first provided between the first and second device regions and recessed to form a gap therebetween. The conductive connector is then formed in the gap above the recessed dielectric spacer.Type: ApplicationFiled: September 7, 2006Publication date: March 13, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Byeong Y. Kim, Xiaomeng Chen, Yoichi Otani
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Publication number: 20080057647Abstract: The present invention provides two-transistor silicon-oxide-nitride-oxide-semiconductor (2-Tr SONOS) non-volatile memory cells with randomly accessible storage locations as well as method of fabricating the same. In one embodiment, a 2-Tr SONOS cell is provided in which the select transistor is located with a trench structure having trench depth from 1 to 2 ?m and the memory transistor is located on a surface of a semiconductor substrate adjoining the trench structure. In another embodiment, a 2-Tr SONOS memory cell is provided in which both the select transistor and the memory transistor are located within a trench structure having the depth mentioned above.Type: ApplicationFiled: October 30, 2007Publication date: March 6, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Herbert Ho, Jack Mandelman, Tak Ning, Yoichi Otani
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Patent number: 7230877Abstract: A method for fabricating a semiconductor memory device is described. An insulating layer is disposed on a semiconductor substrate. A matrix of semiconductor memory elements is disposed in the substrate. The semiconductor memory elements include a plurality of contact holes formed in the insulating layer. One contact hole is formed in the insulating layer for each of the semiconductor memory elements. A bit definition region is disposed in the semiconductor substrate underneath each of the contact holes. A contact plug is disposed in each of the contact holes and is in electrical contact with the bit definition region. The bit definition region is configured such that a contact resistance between the semiconductor substrate and the contact plug defines a bit to be stored in the semiconductor memory elements, An evaluation circuit is connected to and evaluates the contact resistance of the semiconductor memory elements.Type: GrantFiled: October 10, 2000Date of Patent: June 12, 2007Assignee: Infineon Technologies AGInventors: Andreas Rusch, Steffen Rothenhäusser, Alexander Truby, Yoichi Otani, Ulrich Zimmermann