Patents by Inventor Yoichiro Tarui
Yoichiro Tarui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160181160Abstract: When a gate insulating film is formed on a silicon carbide substrate, the silicon carbide substrate is first oxidized with an oxidation reactant gas to form the gate insulating film on the surface of the silicon carbide substrate. The silicon carbide substrate on which the gate insulating film has been formed is nitrided with a nitriding reactant gas. The oxidation and the nitriding are performed continuously in the same diffusion furnace while a temperature of 1200° C. to 1300° C. inclusive is maintained.Type: ApplicationFiled: September 14, 2015Publication date: June 23, 2016Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Hideaki YUKI, Kazuo KOBAYASHI, Yoichiro TARUI
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Patent number: 9362391Abstract: It is expected that both reduction of the resistance of a source region and reduction of a leakage current in a gate oxide film be achieved in an MOSFET in a silicon carbide semiconductor device. A leakage current to occur in a gate oxide film of the MOSFET is suppressed by reducing roughness at an interface between a source region and the gate oxide film. If an impurity concentration is to become high at a surface portion of the source region, the gate oxide film is formed by dry oxidation or CVD process. If the gate oxide film is formed by wet oxidation, the impurity concentration at the surface portion of the source region is controlled at a low level.Type: GrantFiled: September 21, 2011Date of Patent: June 7, 2016Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Yoichiro Tarui, Eisuke Suekawa, Naoki Yutani, Shiro Hino, Naruhisa Miura, Masayuki Imaizumi
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Patent number: 9324806Abstract: A silicon carbide semiconductor device includes: a silicon carbide semiconductor layer of a first conductivity type; a field insulating film formed on a surface of the silicon carbide semiconductor layer; a Schottky electrode formed on the surface of the silicon carbide semiconductor layer on an inner periphery side relative to the field insulating film, the Schottky electrode being formed to overlap onto the field insulating film; a front-surface electrode that covers the Schottky electrode and extends on the field insulating film beyond a peripheral edge of the Schottky electrode; and a terminal well region of a second conductivity type that is formed to be in contact with a part of the Schottky electrode in an upper part of the silicon carbide semiconductor layer and extends in the silicon carbide semiconductor layer on an outer periphery side relative to a peripheral edge of the front-surface electrode.Type: GrantFiled: April 9, 2015Date of Patent: April 26, 2016Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Chihiro Tadokoro, Yoichiro Tarui, Koji Okuno
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Patent number: 9276068Abstract: A silicon oxide film is formed on an epitaxial layer by dry thermal oxidation, an ohmic electrode is formed on a back surface of a SiC substrate, an ohmic junction is formed between the ohmic electrode and the back surface of the SiC substrate by annealing the SiC substrate, the silicon oxide film is removed, and a Schottky electrode is formed on the epitaxial layer. Then, a sintering treatment is performed to form a Schottky junction between the Schottky electrode and the epitaxial layer.Type: GrantFiled: October 3, 2013Date of Patent: March 1, 2016Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Yoshinori Matsuno, Yoichiro Tarui
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Patent number: 9184307Abstract: A silicon carbide semiconductor device includes: a drift layer of the a first conduction type; a guard ring region of a second conduction type formed in annular form in a portion of one surface of the drift layer; a field insulating film formed on the one surface of the drift layer and surrounding the guard ring region; a Schottky electrode covering the guard ring region and the drift layer exposed inside the guard ring region and having an outer peripheral end existing on the field insulating film; and a surface electrode pad on the Schottky electrode, wherein an outer peripheral end of the surface electrode pad comes into contact with the field insulating film over the outer peripheral end of the Schottky electrode.Type: GrantFiled: May 29, 2014Date of Patent: November 10, 2015Assignee: Mitsubishi Electric CorporationInventors: Yoichiro Tarui, Masayuki Imaizumi, Naoki Yutani
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Patent number: 9184306Abstract: A silicon carbide semiconductor device of the present invention comprises a silicon carbide drift layer formed on a silicon carbide substrate, a P-type region formed in a surface layer of the silicon carbide drift layer, and a Schottky electrode formed above the silicon carbide drift layer correspondingly to a forming portion of the P-type region. The P-type region is formed of a plurality of unit cells arranged therein. Each of the unit cells has at least a first distribution region in which the P-type impurity is distributed at first concentration and a second distribution region in which the P-type impurity is distributed at second concentration higher than the first concentration. With this structure, it is possible to provide a silicon carbide semiconductor device in which a sufficient breakdown voltage can be achieved with less number of ion implantations.Type: GrantFiled: June 28, 2013Date of Patent: November 10, 2015Assignee: Mitsubishi Electric CorporationInventors: Takeshi Kitani, Yoichiro Tarui
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Publication number: 20150318357Abstract: A silicon carbide semiconductor device includes: a silicon carbide semiconductor layer of a first conductivity type; a field insulating film formed on a surface of the silicon carbide semiconductor layer; a Schottky electrode formed on the surface of the silicon carbide semiconductor layer on an inner periphery side relative to the field insulating film, the Schottky electrode being formed to overlap onto the field insulating film; a front-surface electrode that covers the Schottky electrode and extends on the field insulating film beyond a peripheral edge of the Schottky electrode; and a terminal well region of a second conductivity type that is formed to be in contact with a part of the Schottky electrode in an upper part of the silicon carbide semiconductor layer and extends in the silicon carbide semiconductor layer on an outer periphery side relative to a peripheral edge of the front-surface electrode.Type: ApplicationFiled: April 9, 2015Publication date: November 5, 2015Applicant: Mitsubishi Electric CorporationInventors: Chihiro TADOKORO, Yoichiro TARUI, Koji OKUNO
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Patent number: 9159585Abstract: A method of manufacturing a semiconductor device according to the present invention includes the steps of (b) forming, on a back face of a dummy substrate and back faces of a plurality of semiconductor substrates, inorganic films having such thicknesses as to be resistant to a temperature of a thermal oxidizing treatment or a heat treatment and to sufficiently decrease an amount of oxidation or reducing gaseous species to reach the back faces of the dummy substrate and the plurality of semiconductor substrates, (c) disposing the dummy substrate and the plurality of semiconductor substrates in a lamination with surfaces turned in the same direction at an interval from each other, and (d) carrying out a thermal oxidizing treatment or post annealing over the surfaces of the semiconductor substrates in an oxidation gas atmosphere or a reducing gas atmosphere after the steps (b) and (c).Type: GrantFiled: November 4, 2013Date of Patent: October 13, 2015Assignee: Mitsubishi Electric CorporationInventors: Toshikazu Tanioka, Yoichiro Tarui, Kazuo Kobayashi, Hideaki Yuki, Yosuke Setoguchi
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Publication number: 20150243753Abstract: A MOSFET cell of a semiconductor device includes a polysilicon gate electrode and an n+-source region formed in an upper portion of an n?-drift layer. An interlayer insulating film covers the gate electrode. An Al source electrode extends on the interlayer insulating film. An Al gate pad is connected to the gate electrode. A barrier metal layer that prevents diffusion of aluminum is interposed between the source electrode and the interlayer insulating film, and between the gate pad and the gate electrode.Type: ApplicationFiled: May 1, 2015Publication date: August 27, 2015Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Eisuke SUEKAWA, Yasunori ORITSUKI, Yoichiro TARUI
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Patent number: 9041007Abstract: A MOSFET cell of a semiconductor device includes a polysilicon gate electrode and an n+-source region formed in an upper portion of an n?-drift layer. An interlayer insulating film covers the gate electrode. An Al source electrode extends on the interlayer insulating film. An Al gate pad is connected to the gate electrode. A barrier metal layer that prevents diffusion of aluminum is interposed between the source electrode and the interlayer insulating film, and between the gate pad and the gate electrode.Type: GrantFiled: November 18, 2011Date of Patent: May 26, 2015Assignee: Mitsubishi Electric CorporationInventors: Eisuke Suekawa, Yasunori Oritsuki, Yoichiro Tarui
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Patent number: 8987817Abstract: A semiconductor device of the present invention includes: a semiconductor substrate of a first conductive type; an epitaxial layer of the first conductive type formed on the semiconductor substrate and having a protrusion formed on a surface thereof; a well region of a second conductive type formed on the surface of the epitaxial layer at each side of the protrusion; a source region of the first conductive type selectively formed in a surface of the well region; a gate insulating film formed so as to cover at least the protrusion and the surface of the well region; and a gate electrode formed on a part of the gate insulating film corresponding to the protrusion. The gate insulating film is thicker in a region thereof corresponding to an upper surface of the protrusion than the other regions thereof.Type: GrantFiled: August 3, 2011Date of Patent: March 24, 2015Assignee: Mitsubishi Electric CorporationInventor: Yoichiro Tarui
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Patent number: 8987105Abstract: A method of manufacturing an SiC semiconductor device according to the present invention includes the steps of (a) by using a single mask, etching regions of an SiC semiconductor layer which serve as an impurities implantation region and a mark region, to form recesses, (b) by using the same mask as in the step (a), performing ion-implantation in the recesses of the regions which serve as the impurities implantation region and the mark region, at least from an oblique direction relative to a surface of the SiC semiconductor layer and (c) positioning another mask based on the recess of the region which serves as the impurities implantation region or the mark region, and performing well implantation in a region containing the impurities implantation region.Type: GrantFiled: April 17, 2013Date of Patent: March 24, 2015Assignee: Mitsubishi Electric CorporationInventors: Noriaki Tsuchiya, Yoichiro Tarui
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Publication number: 20150060882Abstract: A silicon carbide semiconductor device includes: a drift layer of the a first conduction type; a guard ring region of a second conduction type formed in annular form in a portion of one surface of the drift layer; a field insulating film formed on the one surface of the drift layer and surrounding the guard ring region; a Schottky electrode covering the guard ring region and the drift layer exposed inside the guard ring region and having an outer peripheral end existing on the field insulating film; and a surface electrode pad on the Schottky electrode, wherein an outer peripheral end of the surface electrode pad comes into contact with the field insulating film over the outer peripheral end of the Schottky electrode.Type: ApplicationFiled: May 29, 2014Publication date: March 5, 2015Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Yoichiro TARUI, Masayuki IMAIZUMI, Naoki YUTANI
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Publication number: 20150014705Abstract: An optical fiber is provided between a photodiode and a semiconductor active portion of a wide gap semiconductor element forming portion such that emitted light at the time of light emission of the semiconductor active portion of the wide gap semiconductor element forming portion is incident from an incident surface of the optical fiber, and is received from an emitting surface to the photodiode through the optical fiber. Specifically, the incident surface of the optical fiber is arranged so as to be opposed to a side surface portion of the wide gap semiconductor element forming portion, so that the emitted light at the time of light emission of the wide gap semiconductor element is incident on the incident surface.Type: ApplicationFiled: March 24, 2014Publication date: January 15, 2015Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Naoto KAGUCHI, Yoichiro TARUI
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Patent number: 8932944Abstract: In the manufacture of a silicon carbide semiconductor device having a termination region being a JTE region or FLR, the margin of the amount of etching for removing a damage layer formed in the surface of the termination region is enlarged. A silicon carbide semiconductor device has a termination region being a JTE (Junction Termination Extension) region or an FLR (Field Limiting Ring) at a termination of the semiconductor elements. The termination region is formed by one step of ion implantation in which the kind of impurity and the implant energy are fixed. In the impurity concentration profile of the termination region in the depth direction, the concentration peak in the shallowest position is in a position deeper than 0.35 ?m from the surface, and the concentration in the surface portion is not more than one-tenth of the shallowest concentration peak.Type: GrantFiled: July 24, 2013Date of Patent: January 13, 2015Assignee: Mitsubishi Electric CorporationInventors: Yoichiro Tarui, Naoto Kaguchi, Takuyo Nakamura
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Publication number: 20140242815Abstract: A method of manufacturing a semiconductor device according to the present invention includes the steps of (b) forming, on a back face of a dummy substrate and back faces of a plurality of semiconductor substrates, inorganic films having such thicknesses as to be resistant to a temperature of a thermal oxidizing treatment or a heat treatment and to sufficiently decrease an amount of oxidation or reducing gaseous species to reach the back faces of the dummy substrate and the plurality of semiconductor substrates, (c) disposing the dummy substrate and the plurality of semiconductor substrates in a lamination with surfaces turned in the same direction at an interval from each other, and (d) carrying out a thermal oxidizing treatment or post annealing over the surfaces of the semiconductor substrates in an oxidation gas atmosphere or a reducing gas atmosphere after the steps (b) and (c).Type: ApplicationFiled: November 4, 2013Publication date: August 28, 2014Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Toshikazu TANIOKA, Yoichiro TARUI, Kazuo KOBAYASHI, Hideaki YUKI, Yosuke SETOGUCHI
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Patent number: 8809969Abstract: A semiconductor device using one or more guard rings includes a p-type guard ring region surrounding a pn junction region, an insulating film covering the p-type guard ring region, one or more conductive films electrically connected with the p-type guard ring region through one or more contact holes made in the insulating film, and a semi-insulating film covering the insulating film and the conductive films. Thus, a desired breakdown voltage characteristic can be ensured even if a foreign matter or the like adheres to a surface of the conductive films.Type: GrantFiled: December 31, 2009Date of Patent: August 19, 2014Assignee: Mitsubishi Electric CorporationInventors: Yoichiro Tarui, Atsushi Narazaki, Ryoichi Fujii
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Publication number: 20140210008Abstract: A semiconductor device includes an n-type drift layer formed on a main surface of a semiconductor substrate, a plurality of p-type well regions formed selectively in an upper layer portion of the drift layer, an n-type source region formed in a surface of the p-type well region, and a p-type contact region which is shallower than the source region formed in the surface of the p-type well region adjacent to the source region. Moreover, the semiconductor device includes an n-type additional region formed in contact with a bottom surface of the p-type well region in a position corresponding to below the contact region and deeper than the p-type well region.Type: ApplicationFiled: December 31, 2013Publication date: July 31, 2014Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Yasunori ORITSUKI, Yoichiro TARUI
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Publication number: 20140191251Abstract: It is expected that both reduction of the resistance of a source region and reduction of a leakage current in a gate oxide film be achieved in an MOSFET in a silicon carbide semiconductor device. A leakage current to occur in a gate oxide film of the MOSFET is suppressed by reducing roughness at an interface between a source region and the gate oxide film. If an impurity concentration is to become high at a surface portion of the source region, the gate oxide film is formed by dry oxidation or CVD process. If the gate oxide film is formed by wet oxidation, the impurity concentration at the surface portion of the source region is controlled at a low level.Type: ApplicationFiled: September 21, 2011Publication date: July 10, 2014Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Yoichiro Tarui, Eisuke Suekawa, Naoki Yutani, Shiro Hino, Naruhisa Miura, Masayuki Imaizumi
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Patent number: 8685848Abstract: A silicon oxide film is formed on an epitaxial layer by dry thermal oxidation, an ohmic electrode is formed on a back surface of a SiC substrate, an ohmic junction is formed between the ohmic electrode and the back surface of the SiC substrate by annealing the SiC substrate, the silicon oxide film is removed, and a Schottky electrode is formed on the epitaxial layer. Then, a sintering treatment is performed to form a Schottky junction between the Schottky electrode and the epitaxial layer.Type: GrantFiled: January 23, 2012Date of Patent: April 1, 2014Assignee: Mitsubishi Electric CorporationInventors: Yoshinori Matsuno, Yoichiro Tarui